gdb/tic6x-tdep.c - gdb

Global variables defined

Data types defined

Functions defined

Macros defined

Source code

  1. /* Target dependent code for GDB on TI C6x systems.

  3.    Copyright (C) 2010-2015 Free Software Foundation, Inc.
  4.    Contributed by Andrew Jenner <andrew@codesourcery.com>
  5.    Contributed by Yao Qi <yao@codesourcery.com>

  7.    This file is part of GDB.

  9.    This program is free software; you can redistribute it and/or modify
  10.    it under the terms of the GNU General Public License as published by
  11.    the Free Software Foundation; either version 3 of the License, or
  12.    (at your option) any later version.

  14.    This program is distributed in the hope that it will be useful,
  15.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17.    GNU General Public License for more details.

  19.    You should have received a copy of the GNU General Public License
  20.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  22. #include "defs.h"
  23. #include "frame.h"
  24. #include "frame-unwind.h"
  25. #include "frame-base.h"
  26. #include "trad-frame.h"
  27. #include "dwarf2-frame.h"
  28. #include "symtab.h"
  29. #include "inferior.h"
  30. #include "gdbtypes.h"
  31. #include "gdbcore.h"
  32. #include "gdbcmd.h"
  33. #include "target.h"
  34. #include "dis-asm.h"
  35. #include "regcache.h"
  36. #include "value.h"
  37. #include "symfile.h"
  38. #include "arch-utils.h"
  39. #include "floatformat.h"
  40. #include "glibc-tdep.h"
  41. #include "infcall.h"
  42. #include "regset.h"
  43. #include "tramp-frame.h"
  44. #include "linux-tdep.h"
  45. #include "solib.h"
  46. #include "objfiles.h"
  47. #include "osabi.h"
  48. #include "tic6x-tdep.h"
  49. #include "language.h"
  50. #include "target-descriptions.h"

  52. #include "features/tic6x-c64xp.c"
  53. #include "features/tic6x-c64x.c"
  54. #include "features/tic6x-c62x.c"

  56. ‌#define TIC6X_OPCODE_SIZE 4
  57. ‌#define TIC6X_FETCH_PACKET_SIZE 32

  59. ‌#define INST_S_BIT(INST) ((INST >> 1) & 1)
  60. ‌#define INST_X_BIT(INST) ((INST >> 12) & 1)

  62. ‌const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 };
  63. ‌const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 };

  65. ‌struct tic6x_unwind_cache
  66. {
  67.   /* The frame's base, optionally used by the high-level debug info.  */
  68.   CORE_ADDR base;

  70.   /* The previous frame's inner most stack address.  Used as this
  71.      frame ID's stack_addr.  */
  72.   CORE_ADDR cfa;

  74.   /* The address of the first instruction in this function */
  75.   CORE_ADDR pc;

  77.   /* Which register holds the return address for the frame.  */
  78.   int return_regnum;

  80.   /* The offset of register saved on stack.  If register is not saved, the
  81.      corresponding element is -1.  */
  82.   CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS];
  83. };


  86. /* Name of TI C6x core registers.  */
  87. ‌static const char *const tic6x_register_names[] =
  88. {
  89.   "A0",  "A1",  "A2",  "A3",  /*  0  1  2  3 */
  90.   "A4",  "A5",  "A6",  "A7",  /*  4  5  6  7 */
  91.   "A8",  "A9",  "A10", "A11", /*  8  9 10 11 */
  92.   "A12", "A13", "A14", "A15", /* 12 13 14 15 */
  93.   "B0",  "B1",  "B2",  "B3",  /* 16 17 18 19 */
  94.   "B4",  "B5",  "B6",  "B7",  /* 20 21 22 23 */
  95.   "B8",  "B9",  "B10", "B11", /* 24 25 26 27 */
  96.   "B12", "B13", "B14", "B15", /* 28 29 30 31 */
  97.   "CSR", "PC",                /* 32 33       */
  98. };

  100. /* This array maps the arguments to the register number which passes argument
  101.    in function call according to C6000 ELF ABI.  */
  102. ‌static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };

  104. /* This is the implementation of gdbarch method register_name.  */

  106. static const char *
  107. ‌tic6x_register_name (struct gdbarch *gdbarch, int regno)
  108. {
  109.   if (regno < 0)
  110.     return NULL;

  112.   if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
  113.     return tdesc_register_name (gdbarch, regno);
  114.   else if (regno >= ARRAY_SIZE (tic6x_register_names))
  115.     return "";
  116.   else
  117.     return tic6x_register_names[regno];
  118. }

  120. /* This is the implementation of gdbarch method register_type.  */

  122. static struct type *
  123. ‌tic6x_register_type (struct gdbarch *gdbarch, int regno)
  124. {

  126.   if (regno == TIC6X_PC_REGNUM)
  127.     return builtin_type (gdbarch)->builtin_func_ptr;
  128.   else
  129.     return builtin_type (gdbarch)->builtin_uint32;
  130. }

  132. static void
  133. ‌tic6x_setup_default (struct tic6x_unwind_cache *cache)
  134. {
  135.   int i;

  137.   for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
  138.     cache->reg_saved[i] = -1;
  139. }

  141. static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR);
  142. static int tic6x_register_number (int reg, int side, int crosspath);

  144. /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
  145.    Bail out early if CURRENT_PC is reached.  Returns the address of the first
  146.    instruction after the prologue.  */

  148. static CORE_ADDR
  149. ‌tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
  150.                         const CORE_ADDR current_pc,
  151.                         struct tic6x_unwind_cache *cache,
  152.                         struct frame_info *this_frame)
  153. {
  154.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  155.   unsigned long inst;
  156.   unsigned int src_reg, base_reg, dst_reg;
  157.   int i;
  158.   CORE_ADDR pc = start_pc;
  159.   CORE_ADDR return_pc = start_pc;
  160.   int frame_base_offset_to_sp = 0;
  161.   /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'.  */
  162.   int non_stw_insn_counter = 0;

  164.   if (start_pc >= current_pc)
  165.     return_pc = current_pc;

  167.   cache->base = 0;

  169.   /* The landmarks in prologue is one or two SUB instructions to SP.
  170.      Instructions on setting up dsbt are in the last part of prologue, if
  171.      needed.  In maxim, prologue can be divided to three parts by two
  172.      `sub sp, xx, sp' insns.  */

  174.   /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp',  in which, the
  175.      2nd one is optional.  */
  176.   while (pc < current_pc)
  177.     {
  178.       int offset = 0;

  180.       unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);

  182.       if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0
  183.           || (inst & 0x0ffc) == 0x9c0)
  184.         {
  185.           /* SUBAW/SUBAH/SUB, and src1 is ucst 5.  */
  186.           unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
  187.                                                      INST_S_BIT (inst), 0);
  188.           unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f,
  189.                                                     INST_S_BIT (inst), 0);

  191.           if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM)
  192.             {
  193.               /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
  194.                  offset.  The constant offset is decoded in bit 13-17 in all
  195.                  these three kinds of instructions.  */
  196.               unsigned int ucst5 = (inst >> 13) & 0x1f;

  198.               if ((inst & 0x1ffc) == 0x1dc0)        /* SUBAW */
  199.                 frame_base_offset_to_sp += ucst5 << 2;
  200.               else if ((inst & 0x1ffc) == 0x1bc0)        /* SUBAH */
  201.                 frame_base_offset_to_sp += ucst5 << 1;
  202.               else if ((inst & 0x0ffc) == 0x9c0)        /* SUB */
  203.                 frame_base_offset_to_sp += ucst5;
  204.               else
  205.                 gdb_assert_not_reached ("unexpected instruction");

  207.               return_pc = pc + 4;
  208.             }
  209.         }
  210.       else if ((inst & 0x174) == 0x74)        /* stw SRC, *+b15(uconst) */
  211.         {
  212.           /* The y bit determines which file base is read from.  */
  213.           base_reg = tic6x_register_number ((inst >> 18) & 0x1f,
  214.                                             (inst >> 7) & 1, 0);

  216.           if (base_reg == TIC6X_SP_REGNUM)
  217.             {
  218.               src_reg = tic6x_register_number ((inst >> 23) & 0x1f,
  219.                                                INST_S_BIT (inst), 0);

  221.               cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2;

  223.               return_pc = pc + 4;
  224.             }
  225.           non_stw_insn_counter = 0;
  226.         }
  227.       else
  228.         {
  229.           non_stw_insn_counter++;
  230.           /* Following instruction sequence may be emitted in prologue:

  232.              <+0>: subah .D2 b15,28,b15
  233.              <+4>: or .L2X 0,a4,b0
  234.              <+8>: || stw .D2T2 b14,*+b15(56)
  235.              <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
  236.              <+16>:|| stw .D2T1 a10,*+b15(48)
  237.              <+20>:stw .D2T2 b3,*+b15(52)
  238.              <+24>:stw .D2T1 a4,*+b15(40)

  240.              we should look forward for next instruction instead of breaking loop
  241.              here.  So far, we allow almost two sequential non-stw instructions
  242.              in prologue.  */
  243.           if (non_stw_insn_counter >= 2)
  244.             break;
  245.         }


  248.       pc += 4;
  249.     }
  250.   /* Step 2: Skip insn on setting up dsbt if it is.  Usually, it looks like,
  251.      ldw .D2T2 *+b14(0),b14 */
  252.   inst = tic6x_fetch_instruction (gdbarch, pc);
  253.   /* The s bit determines which file dst will be loaded into, same effect as
  254.      other places.  */
  255.   dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0);
  256.   /* The y bit (bit 7), instead of s bit, determines which file base be
  257.      used.  */
  258.   base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0);

  260.   if ((inst & 0x164) == 0x64        /* ldw */
  261.       && dst_reg == TIC6X_DP_REGNUM        /* dst is B14 */
  262.       && base_reg == TIC6X_DP_REGNUM)        /* baseR is B14 */
  263.     {
  264.       return_pc = pc + 4;
  265.     }

  267.   if (this_frame)
  268.     {
  269.       cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);

  271.       if (cache->reg_saved[TIC6X_FP_REGNUM] != -1)
  272.         {
  273.           /* If the FP now holds an offset from the CFA then this is a frame
  274.              which uses the frame pointer.  */

  276.           cache->cfa = get_frame_register_unsigned (this_frame,
  277.                                                     TIC6X_FP_REGNUM);
  278.         }
  279.       else
  280.         {
  281.           /* FP doesn't hold an offset from the CFA.  If SP still holds an
  282.              offset from the CFA then we might be in a function which omits
  283.              the frame pointer.  */

  285.           cache->cfa = cache->base + frame_base_offset_to_sp;
  286.         }
  287.     }

  289.   /* Adjust all the saved registers such that they contain addresses
  290.      instead of offsets.  */
  291.   for (i = 0; i < TIC6X_NUM_CORE_REGS; i++)
  292.     if (cache->reg_saved[i] != -1)
  293.       cache->reg_saved[i] = cache->base + cache->reg_saved[i];

  295.   return return_pc;
  296. }

  298. /* This is the implementation of gdbarch method skip_prologue.  */

  300. static CORE_ADDR
  301. ‌tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
  302. {
  303.   CORE_ADDR func_addr;
  304.   struct tic6x_unwind_cache cache;

  306.   /* See if we can determine the end of the prologue via the symbol table.
  307.      If so, then return either PC, or the PC after the prologue, whichever is
  308.      greater.  */
  309.   if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
  310.     {
  311.       CORE_ADDR post_prologue_pc
  312.         = skip_prologue_using_sal (gdbarch, func_addr);
  313.       if (post_prologue_pc != 0)
  314.         return max (start_pc, post_prologue_pc);
  315.     }

  317.   /* Can't determine prologue from the symbol table, need to examine
  318.      instructions.  */
  319.   return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache,
  320.                                  NULL);
  321. }

  323. /* This is the implementation of gdbarch method breakpiont_from_pc.  */

  325. static const gdb_byte *
  326. ‌tic6x_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
  327.                           int *bp_size)
  328. {
  329.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  331.   *bp_size = 4;

  333.   if (tdep == NULL || tdep->breakpoint == NULL)
  334.     {
  335.       if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch))
  336.         return tic6x_bkpt_illegal_opcode_be;
  337.       else
  338.         return tic6x_bkpt_illegal_opcode_le;
  339.     }
  340.   else
  341.     return tdep->breakpoint;
  342. }

  344. /* This is the implementation of gdbarch method print_insn.  */

  346. static int
  347. ‌tic6x_print_insn (bfd_vma memaddr, disassemble_info *info)
  348. {
  349.   return print_insn_tic6x (memaddr, info);
  350. }

  352. static void
  353. ‌tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
  354.                              struct dwarf2_frame_state_reg *reg,
  355.                              struct frame_info *this_frame)
  356. {
  357.   /* Mark the PC as the destination for the return address.  */
  358.   if (regnum == gdbarch_pc_regnum (gdbarch))
  359.     reg->how = DWARF2_FRAME_REG_RA;

  361.   /* Mark the stack pointer as the call frame address.  */
  362.   else if (regnum == gdbarch_sp_regnum (gdbarch))
  363.     reg->how = DWARF2_FRAME_REG_CFA;

  365.   /* The above was taken from the default init_reg in dwarf2-frame.c
  366.      while the below is c6x specific.  */

  368.   /* Callee save registers.  The ABI designates A10-A15 and B10-B15 as
  369.      callee-save.  */
  370.   else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31))
  371.     reg->how = DWARF2_FRAME_REG_SAME_VALUE;
  372.   else
  373.     /* All other registers are caller-save.  */
  374.     reg->how = DWARF2_FRAME_REG_UNDEFINED;
  375. }

  377. /* This is the implementation of gdbarch method unwind_pc.  */

  379. static CORE_ADDR
  380. ‌tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
  381. {
  382.   gdb_byte buf[8];

  384.   frame_unwind_register (next_frame,  TIC6X_PC_REGNUM, buf);
  385.   return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
  386. }

  388. /* This is the implementation of gdbarch method unwind_sp.  */

  390. static CORE_ADDR
  391. ‌tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
  392. {
  393.   return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM);
  394. }


  397. /* Frame base handling.  */

  399. static struct tic6x_unwind_cache*
  400. ‌tic6x_frame_unwind_cache (struct frame_info *this_frame,
  401.                           void **this_prologue_cache)
  402. {
  403.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  404.   CORE_ADDR current_pc;
  405.   struct tic6x_unwind_cache *cache;

  407.   if (*this_prologue_cache)
  408.     return *this_prologue_cache;

  410.   cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);
  411.   (*this_prologue_cache) = cache;

  413.   cache->return_regnum = TIC6X_RA_REGNUM;

  415.   tic6x_setup_default (cache);

  417.   cache->pc = get_frame_func (this_frame);
  418.   current_pc = get_frame_pc (this_frame);

  420.   /* Prologue analysis does the rest...  */
  421.   if (cache->pc != 0)
  422.     tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);

  424.   return cache;
  425. }

  427. static void
  428. ‌tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache,
  429.                      struct frame_id *this_id)
  430. {
  431.   struct tic6x_unwind_cache *cache =
  432.     tic6x_frame_unwind_cache (this_frame, this_cache);

  434.   /* This marks the outermost frame.  */
  435.   if (cache->base == 0)
  436.     return;

  438.   (*this_id) = frame_id_build (cache->cfa, cache->pc);
  439. }

  441. static struct value *
  442. ‌tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache,
  443.                            int regnum)
  444. {
  445.   struct tic6x_unwind_cache *cache =
  446.     tic6x_frame_unwind_cache (this_frame, this_cache);

  448.   gdb_assert (regnum >= 0);

  450.   /* The PC of the previous frame is stored in the RA register of
  451.      the current frame.  Frob regnum so that we pull the value from
  452.      the correct place.  */
  453.   if (regnum == TIC6X_PC_REGNUM)
  454.     regnum = cache->return_regnum;

  456.   if (regnum == TIC6X_SP_REGNUM && cache->cfa)
  457.     return frame_unwind_got_constant (this_frame, regnum, cache->cfa);

  459.   /* If we've worked out where a register is stored then load it from
  460.      there.  */
  461.   if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1)
  462.     return frame_unwind_got_memory (this_frame, regnum,
  463.                                     cache->reg_saved[regnum]);

  465.   return frame_unwind_got_register (this_frame, regnum, regnum);
  466. }

  468. static CORE_ADDR
  469. ‌tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache)
  470. {
  471.   struct tic6x_unwind_cache *info
  472.     = tic6x_frame_unwind_cache (this_frame, this_cache);
  473.   return info->base;
  474. }

  476. ‌static const struct frame_unwind tic6x_frame_unwind =
  477. {
  478.   NORMAL_FRAME,
  479.   default_frame_unwind_stop_reason,
  480.   tic6x_frame_this_id,
  481.   tic6x_frame_prev_register,
  482.   NULL,
  483.   default_frame_sniffer
  484. };

  486. ‌static const struct frame_base tic6x_frame_base =
  487. {
  488.   &tic6x_frame_unwind,
  489.   tic6x_frame_base_address,
  490.   tic6x_frame_base_address,
  491.   tic6x_frame_base_address
  492. };


  495. static struct tic6x_unwind_cache *
  496. ‌tic6x_make_stub_cache (struct frame_info *this_frame)
  497. {
  498.   struct tic6x_unwind_cache *cache;

  500.   cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache);

  502.   cache->return_regnum = TIC6X_RA_REGNUM;

  504.   tic6x_setup_default (cache);

  506.   cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM);

  508.   return cache;
  509. }

  511. static void
  512. ‌tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache,
  513.                     struct frame_id *this_id)
  514. {
  515.   struct tic6x_unwind_cache *cache;

  517.   if (*this_cache == NULL)
  518.     *this_cache = tic6x_make_stub_cache (this_frame);
  519.   cache = *this_cache;

  521.   *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame));
  522. }

  524. static int
  525. ‌tic6x_stub_unwind_sniffer (const struct frame_unwind *self,
  526.                            struct frame_info *this_frame,
  527.                            void **this_prologue_cache)
  528. {
  529.   CORE_ADDR addr_in_block;

  531.   addr_in_block = get_frame_address_in_block (this_frame);
  532.   if (in_plt_section (addr_in_block))
  533.     return 1;

  535.   return 0;
  536. }

  538. ‌static const struct frame_unwind tic6x_stub_unwind =
  539. {
  540.   NORMAL_FRAME,
  541.   default_frame_unwind_stop_reason,
  542.   tic6x_stub_this_id,
  543.   tic6x_frame_prev_register,
  544.   NULL,
  545.   tic6x_stub_unwind_sniffer
  546. };

  548. /* Return the instruction on address PC.  */

  550. static unsigned long
  551. ‌tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc)
  552. {
  553.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  554.   return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order);
  555. }

  557. /* Compute the condition of INST if it is a conditional instruction.  Always
  558.    return 1 if INST is not a conditional instruction.  */

  560. static int
  561. ‌tic6x_condition_true (struct frame_info *frame, unsigned long inst)
  562. {
  563.   int register_number;
  564.   int register_value;
  565.   static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };

  567.   register_number = register_numbers[(inst >> 29) & 7];
  568.   if (register_number == -1)
  569.     return 1;

  571.   register_value = get_frame_register_signed (frame, register_number);
  572.   if ((inst & 0x10000000) != 0)
  573.     return register_value == 0;
  574.   return register_value != 0;
  575. }

  577. /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
  578.    instruction.  */

  580. static int
  581. ‌tic6x_register_number (int reg, int side, int crosspath)
  582. {
  583.   int r = (reg & 15) | ((crosspath ^ side) << 4);
  584.   if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */
  585.     r += 37;
  586.   return r;
  587. }

  589. static int
  590. ‌tic6x_extract_signed_field (int value, int low_bit, int bits)
  591. {
  592.   int mask = (1 << bits) - 1;
  593.   int r = (value >> low_bit) & mask;
  594.   if ((r & (1 << (bits - 1))) != 0)
  595.     r -= mask + 1;
  596.   return r;
  597. }

  599. /* Determine where to set a single step breakpoint.  */

  601. static CORE_ADDR
  602. ‌tic6x_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
  603. {
  604.   struct gdbarch *gdbarch = get_frame_arch (frame);
  605.   unsigned long inst;
  606.   int register_number;
  607.   int last = 0;

  609.   do
  610.     {
  611.       inst = tic6x_fetch_instruction (gdbarch, pc);

  613.       last = !(inst & 1);

  615.       if (inst == TIC6X_INST_SWE)
  616.         {
  617.           struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  619.           if (tdep->syscall_next_pc != NULL)
  620.             return tdep->syscall_next_pc (frame);
  621.         }

  623.       if (tic6x_condition_true (frame, inst))
  624.         {
  625.           if ((inst & 0x0000007c) == 0x00000010)
  626.             {
  627.               /* B with displacement */
  628.               pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
  629.               pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
  630.               break;
  631.             }
  632.           if ((inst & 0x0f83effc) == 0x00000360)
  633.             {
  634.               /* B with register */

  636.               register_number = tic6x_register_number ((inst >> 18) & 0x1f,
  637.                                                        INST_S_BIT (inst),
  638.                                                        INST_X_BIT (inst));
  639.               pc = get_frame_register_unsigned (frame, register_number);
  640.               break;
  641.             }
  642.           if ((inst & 0x00001ffc) == 0x00001020)
  643.             {
  644.               /* BDEC */
  645.               register_number = tic6x_register_number ((inst >> 23) & 0x1f,
  646.                                                        INST_S_BIT (inst), 0);
  647.               if (get_frame_register_signed (frame, register_number) >= 0)
  648.                 {
  649.                   pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
  650.                   pc += tic6x_extract_signed_field (inst, 7, 10) << 2;
  651.                 }
  652.               break;
  653.             }
  654.           if ((inst & 0x00001ffc) == 0x00000120)
  655.             {
  656.               /* BNOP with displacement */
  657.               pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
  658.               pc += tic6x_extract_signed_field (inst, 16, 12) << 2;
  659.               break;
  660.             }
  661.           if ((inst & 0x0f830ffe) == 0x00800362)
  662.             {
  663.               /* BNOP with register */
  664.               register_number = tic6x_register_number ((inst >> 18) & 0x1f,
  665.                                                        1, INST_X_BIT (inst));
  666.               pc = get_frame_register_unsigned (frame, register_number);
  667.               break;
  668.             }
  669.           if ((inst & 0x00001ffc) == 0x00000020)
  670.             {
  671.               /* BPOS */
  672.               register_number = tic6x_register_number ((inst >> 23) & 0x1f,
  673.                                                        INST_S_BIT (inst), 0);
  674.               if (get_frame_register_signed (frame, register_number) >= 0)
  675.                 {
  676.                   pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
  677.                   pc += tic6x_extract_signed_field (inst, 13, 10) << 2;
  678.                 }
  679.               break;
  680.             }
  681.           if ((inst & 0xf000007c) == 0x10000010)
  682.             {
  683.               /* CALLP */
  684.               pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1);
  685.               pc += tic6x_extract_signed_field (inst, 7, 21) << 2;
  686.               break;
  687.             }
  688.         }
  689.       pc += TIC6X_OPCODE_SIZE;
  690.     }
  691.   while (!last);
  692.   return pc;
  693. }

  695. /* This is the implementation of gdbarch method software_single_step.  */

  697. static int
  698. ‌tic6x_software_single_step (struct frame_info *frame)
  699. {
  700.   struct gdbarch *gdbarch = get_frame_arch (frame);
  701.   struct address_space *aspace = get_frame_address_space (frame);
  702.   CORE_ADDR next_pc = tic6x_get_next_pc (frame, get_frame_pc (frame));

  704.   insert_single_step_breakpoint (gdbarch, aspace, next_pc);

  706.   return 1;
  707. }

  709. /* This is the implementation of gdbarch method frame_align.  */

  711. static CORE_ADDR
  712. ‌tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
  713. {
  714.   return align_down (addr, 8);
  715. }

  717. /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
  718.    value into VALBUF.  */

  720. static void
  721. ‌tic6x_extract_return_value (struct type *valtype, struct regcache *regcache,
  722.                             enum bfd_endian byte_order, gdb_byte *valbuf)
  723. {
  724.   int len = TYPE_LENGTH (valtype);

  726.   /* pointer types are returned in register A4,
  727.      up to 32-bit types in A4
  728.      up to 64-bit types in A5:A4  */
  729.   if (len <= 4)
  730.     {
  731.       /* In big-endian,
  732.          - one-byte structure or union occupies the LSB of single even register.
  733.          - for two-byte structure or union, the first byte occupies byte 1 of
  734.          register and the second byte occupies byte 0.
  735.          so, we read the contents in VAL from the LSBs of register.  */
  736.       if (len < 3 && byte_order == BFD_ENDIAN_BIG)
  737.         regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
  738.                                    valbuf);
  739.       else
  740.         regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
  741.     }
  742.   else if (len <= 8)
  743.     {
  744.       /* For a 5-8 byte structure or union in big-endian, the first byte
  745.          occupies byte 3 (the MSB) of the upper (odd) register and the
  746.          remaining bytes fill the decreasingly significant bytes.  5-7
  747.          byte structures or unions have padding in the LSBs of the
  748.          lower (even) register.  */
  749.       if (byte_order == BFD_ENDIAN_BIG)
  750.         {
  751.           regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4);
  752.           regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf);
  753.         }
  754.       else
  755.         {
  756.           regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf);
  757.           regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4);
  758.         }
  759.     }
  760. }

  762. /* Write into appropriate registers a function return value
  763.    of type TYPE, given in virtual format.  */

  765. static void
  766. ‌tic6x_store_return_value (struct type *valtype, struct regcache *regcache,
  767.                           enum bfd_endian byte_order, const gdb_byte *valbuf)
  768. {
  769.   int len = TYPE_LENGTH (valtype);

  771.   /* return values of up to 8 bytes are returned in A5:A4 */

  773.   if (len <= 4)
  774.     {
  775.       if (len < 3 && byte_order == BFD_ENDIAN_BIG)
  776.         regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len,
  777.                                     valbuf);
  778.       else
  779.         regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
  780.     }
  781.   else if (len <= 8)
  782.     {
  783.       if (byte_order == BFD_ENDIAN_BIG)
  784.         {
  785.           regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4);
  786.           regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf);
  787.         }
  788.       else
  789.         {
  790.           regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf);
  791.           regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4);
  792.         }
  793.     }
  794. }

  796. /* This is the implementation of gdbarch method return_value.  */

  798. static enum return_value_convention
  799. ‌tic6x_return_value (struct gdbarch *gdbarch, struct value *function,
  800.                     struct type *type, struct regcache *regcache,
  801.                     gdb_byte *readbuf, const gdb_byte *writebuf)
  802. {
  803.   /* In C++, when function returns an object, even its size is small
  804.      enough, it stii has to be passed via reference, pointed by register
  805.      A3.  */
  806.   if (current_language->la_language == language_cplus)
  807.     {
  808.       if (type != NULL)
  809.         {
  810.           CHECK_TYPEDEF (type);
  811.           if (language_pass_by_reference (type))
  812.             return RETURN_VALUE_STRUCT_CONVENTION;
  813.         }
  814.     }

  816.   if (TYPE_LENGTH (type) > 8)
  817.     return RETURN_VALUE_STRUCT_CONVENTION;

  819.   if (readbuf)
  820.     tic6x_extract_return_value (type, regcache,
  821.                                 gdbarch_byte_order (gdbarch), readbuf);
  822.   if (writebuf)
  823.     tic6x_store_return_value (type, regcache,
  824.                               gdbarch_byte_order (gdbarch), writebuf);

  826.   return RETURN_VALUE_REGISTER_CONVENTION;
  827. }

  829. /* This is the implementation of gdbarch method dummy_id.  */

  831. static struct frame_id
  832. ‌tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
  833. {
  834.   return frame_id_build
  835.     (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM),
  836.      get_frame_pc (this_frame));
  837. }

  839. /* Get the alignment requirement of TYPE.  */

  841. static int
  842. ‌tic6x_arg_type_alignment (struct type *type)
  843. {
  844.   int len = TYPE_LENGTH (check_typedef (type));
  845.   enum type_code typecode = TYPE_CODE (check_typedef (type));

  847.   if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
  848.     {
  849.       /* The stack alignment of a structure (and union) passed by value is the
  850.          smallest power of two greater than or equal to its size.
  851.          This cannot exceed 8 bytes, which is the largest allowable size for
  852.          a structure passed by value.  */

  854.       if (len <= 2)
  855.         return len;
  856.       else if (len <= 4)
  857.         return 4;
  858.       else if (len <= 8)
  859.         return 8;
  860.       else
  861.         gdb_assert_not_reached ("unexpected length of data");
  862.     }
  863.   else
  864.     {
  865.       if (len <= 4)
  866.         return 4;
  867.       else if (len == 8)
  868.         {
  869.           if (typecode == TYPE_CODE_COMPLEX)
  870.             return 4;
  871.           else
  872.             return 8;
  873.         }
  874.       else if (len == 16)
  875.         {
  876.           if (typecode == TYPE_CODE_COMPLEX)
  877.             return 8;
  878.           else
  879.             return 16;
  880.         }
  881.       else
  882.         internal_error (__FILE__, __LINE__, _("unexpected length %d of type"),
  883.                         len);
  884.     }
  885. }

  887. /* This is the implementation of gdbarch method push_dummy_call.  */

  889. static CORE_ADDR
  890. ‌tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
  891.                        struct regcache *regcache, CORE_ADDR bp_addr,
  892.                        int nargs, struct value **args, CORE_ADDR sp,
  893.                        int struct_return, CORE_ADDR struct_addr)
  894. {
  895.   int argreg = 0;
  896.   int argnum;
  897.   int stack_offset = 4;
  898.   int references_offset = 4;
  899.   CORE_ADDR func_addr = find_function_addr (function, NULL);
  900.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  901.   struct type *func_type = value_type (function);
  902.   /* The first arg passed on stack.  Mostly the first 10 args are passed by
  903.      registers.  */
  904.   int first_arg_on_stack = 10;

  906.   /* Set the return address register to point to the entry point of
  907.      the program, where a breakpoint lies in wait.  */
  908.   regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr);

  910.   /* The caller must pass an argument in A3 containing a destination address
  911.      for the returned value.  The callee returns the object by copying it to
  912.      the address in A3.  */
  913.   if (struct_return)
  914.     regcache_cooked_write_unsigned (regcache, 3, struct_addr);

  916.   /* Determine the type of this function.  */
  917.   func_type = check_typedef (func_type);
  918.   if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
  919.     func_type = check_typedef (TYPE_TARGET_TYPE (func_type));

  921.   gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
  922.               || TYPE_CODE (func_type) == TYPE_CODE_METHOD);

  924.   /* For a variadic C function, the last explicitly declared argument and all
  925.      remaining arguments are passed on the stack.  */
  926.   if (TYPE_VARARGS (func_type))
  927.     first_arg_on_stack = TYPE_NFIELDS (func_type) - 1;

  929.   /* Now make space on the stack for the args.  */
  930.   for (argnum = 0; argnum < nargs; argnum++)
  931.     {
  932.       int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
  933.       if (argnum >= 10 - argreg)
  934.         references_offset += len;
  935.       stack_offset += len;
  936.     }
  937.   sp -= stack_offset;
  938.   /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
  939.      Stack Alignment.  */
  940.   sp = align_down (sp, 8);
  941.   stack_offset = 4;

  943.   /* Now load as many as possible of the first arguments into
  944.      registers, and push the rest onto the stack.  Loop through args
  945.      from first to last.  */
  946.   for (argnum = 0; argnum < nargs; argnum++)
  947.     {
  948.       const gdb_byte *val;
  949.       struct value *arg = args[argnum];
  950.       struct type *arg_type = check_typedef (value_type (arg));
  951.       int len = TYPE_LENGTH (arg_type);
  952.       enum type_code typecode = TYPE_CODE (arg_type);

  954.       val = value_contents (arg);

  956.       /* Copy the argument to general registers or the stack in
  957.          register-sized pieces.  */
  958.       if (argreg < first_arg_on_stack)
  959.         {
  960.           if (len <= 4)
  961.             {
  962.               if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
  963.                 {
  964.                   /* In big-endian,
  965.                      - one-byte structure or union occupies the LSB of single
  966.                      even register.
  967.                      - for two-byte structure or union, the first byte
  968.                      occupies byte 1 of register and the second byte occupies
  969.                      byte 0.
  970.                      so, we write the contents in VAL to the lsp of
  971.                      register.  */
  972.                   if (len < 3 && byte_order == BFD_ENDIAN_BIG)
  973.                     regcache_cooked_write_part (regcache, arg_regs[argreg],
  974.                                                 4 - len, len, val);
  975.                   else
  976.                     regcache_cooked_write (regcache, arg_regs[argreg], val);
  977.                 }
  978.               else
  979.                 {
  980.                   /* The argument is being passed by value in a single
  981.                      register.  */
  982.                   CORE_ADDR regval = extract_unsigned_integer (val, len,
  983.                                                                byte_order);

  985.                   regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
  986.                                                   regval);
  987.                 }
  988.             }
  989.           else
  990.             {
  991.               if (len <= 8)
  992.                 {
  993.                   if (typecode == TYPE_CODE_STRUCT
  994.                       || typecode == TYPE_CODE_UNION)
  995.                     {
  996.                       /* For a 5-8 byte structure or union in big-endian, the
  997.                          first byte occupies byte 3 (the MSB) of the upper (odd)
  998.                          register and the remaining bytes fill the decreasingly
  999.                          significant bytes.  5-7 byte structures or unions have
  1000.                          padding in the LSBs of the lower (even) register.  */
  1001.                       if (byte_order == BFD_ENDIAN_BIG)
  1002.                         {
  1003.                           regcache_cooked_write (regcache,
  1004.                                                  arg_regs[argreg] + 1, val);
  1005.                           regcache_cooked_write_part (regcache,
  1006.                                                       arg_regs[argreg], 0,
  1007.                                                       len - 4, val + 4);
  1008.                         }
  1009.                       else
  1010.                         {
  1011.                           regcache_cooked_write (regcache, arg_regs[argreg],
  1012.                                                  val);
  1013.                           regcache_cooked_write_part (regcache,
  1014.                                                       arg_regs[argreg] + 1, 0,
  1015.                                                       len - 4, val + 4);
  1016.                         }
  1017.                     }
  1018.                   else
  1019.                     {
  1020.                       /* The argument is being passed by value in a pair of
  1021.                          registers.  */
  1022.                       ULONGEST regval = extract_unsigned_integer (val, len,
  1023.                                                                   byte_order);

  1025.                       regcache_cooked_write_unsigned (regcache,
  1026.                                                       arg_regs[argreg],
  1027.                                                       regval);
  1028.                       regcache_cooked_write_unsigned (regcache,
  1029.                                                       arg_regs[argreg] + 1,
  1030.                                                       regval >> 32);
  1031.                     }
  1032.                 }
  1033.               else
  1034.                 {
  1035.                   /* The argument is being passed by reference in a single
  1036.                      register.  */
  1037.                   CORE_ADDR addr;

  1039.                   /* It is not necessary to adjust REFERENCES_OFFSET to
  1040.                      8-byte aligned in some cases, in which 4-byte alignment
  1041.                      is sufficient.  For simplicity, we adjust
  1042.                      REFERENCES_OFFSET to 8-byte aligned.  */
  1043.                   references_offset = align_up (references_offset, 8);

  1045.                   addr = sp + references_offset;
  1046.                   write_memory (addr, val, len);
  1047.                   references_offset += align_up (len, 4);
  1048.                   regcache_cooked_write_unsigned (regcache, arg_regs[argreg],
  1049.                                                   addr);
  1050.                 }
  1051.             }
  1052.           argreg++;
  1053.         }
  1054.       else
  1055.         {
  1056.           /* The argument is being passed on the stack.  */
  1057.           CORE_ADDR addr;

  1059.           /* There are six different cases of alignment, and these rules can
  1060.              be found in tic6x_arg_type_alignment:

  1062.              1) 4-byte aligned if size is less than or equal to 4 byte, such
  1063.              as short, int, struct, union etc.
  1064.              2) 8-byte aligned if size is less than or equal to 8-byte, such
  1065.              as double, long long,
  1066.              3) 4-byte aligned if it is of type _Complex float, even its size
  1067.              is 8-byte.
  1068.              4) 8-byte aligned if it is of type _Complex double or _Complex
  1069.              long double, even its size is 16-byte.  Because, the address of
  1070.              variable is passed as reference.
  1071.              5) struct and union larger than 8-byte are passed by reference, so
  1072.              it is 4-byte aligned.
  1073.              6) struct and union of size between 4 byte and 8 byte varies.
  1074.              alignment of struct variable is the alignment of its first field,
  1075.              while alignment of union variable is the max of all its fields'
  1076.              alignment.  */

  1078.           if (len <= 4)
  1079.             ; /* Default is 4-byte aligned.  Nothing to be done.  */
  1080.           else if (len <= 8)
  1081.             stack_offset = align_up (stack_offset,
  1082.                                      tic6x_arg_type_alignment (arg_type));
  1083.           else if (len == 16)
  1084.             {
  1085.               /* _Complex double or _Complex long double */
  1086.               if (typecode == TYPE_CODE_COMPLEX)
  1087.                 {
  1088.                   /* The argument is being passed by reference on stack.  */
  1089.                   CORE_ADDR addr;
  1090.                   references_offset = align_up (references_offset, 8);

  1092.                   addr = sp + references_offset;
  1093.                   /* Store variable on stack.  */
  1094.                   write_memory (addr, val, len);

  1096.                   references_offset += align_up (len, 4);

  1098.                   /* Pass the address of variable on stack as reference.  */
  1099.                   store_unsigned_integer ((gdb_byte *) val, 4, byte_order,
  1100.                                           addr);
  1101.                   len = 4;

  1103.                 }
  1104.               else
  1105.                 internal_error (__FILE__, __LINE__,
  1106.                                 _("unexpected type %d of arg %d"),
  1107.                                 typecode, argnum);
  1108.             }
  1109.           else
  1110.             internal_error (__FILE__, __LINE__,
  1111.                             _("unexpected length %d of arg %d"), len, argnum);

  1113.           addr = sp + stack_offset;
  1114.           write_memory (addr, val, len);
  1115.           stack_offset += align_up (len, 4);
  1116.         }
  1117.     }

  1119.   regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp);

  1121.   /* Return adjusted stack pointer.  */
  1122.   return sp;
  1123. }

  1125. /* This is the implementation of gdbarch method in_function_epilogue_p.  */

  1127. static int
  1128. ‌tic6x_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
  1129. {
  1130.   unsigned long inst = tic6x_fetch_instruction (gdbarch, pc);
  1131.   /* Normally, the epilogue is composed by instruction `b .S2 b3'.  */
  1132.   if ((inst & 0x0f83effc) == 0x360)
  1133.     {
  1134.       unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f,
  1135.                                                  INST_S_BIT (inst),
  1136.                                                  INST_X_BIT (inst));
  1137.       if (src2 == TIC6X_RA_REGNUM)
  1138.         return 1;
  1139.     }

  1141.   return 0;
  1142. }

  1144. /* This is the implementation of gdbarch method get_longjmp_target.  */

  1146. static int
  1147. ‌tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
  1148. {
  1149.   struct gdbarch *gdbarch = get_frame_arch (frame);
  1150.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1151.   CORE_ADDR jb_addr;
  1152.   gdb_byte buf[4];

  1154.   /* JMP_BUF is passed by reference in A4.  */
  1155.   jb_addr = get_frame_register_unsigned (frame, 4);

  1157.   /* JMP_BUF contains 13 elements of type int, and return address is stored
  1158.      in the last slot.  */
  1159.   if (target_read_memory (jb_addr + 12 * 4, buf, 4))
  1160.     return 0;

  1162.   *pc = extract_unsigned_integer (buf, 4, byte_order);

  1164.   return 1;
  1165. }

  1167. /* This is the implementation of gdbarch method
  1168.    return_in_first_hidden_param_p.  */

  1170. static int
  1171. ‌tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
  1172.                                       struct type *type)
  1173. {
  1174.   return 0;
  1175. }

  1177. static struct gdbarch *
  1178. ‌tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
  1179. {
  1180.   struct gdbarch *gdbarch;
  1181.   struct gdbarch_tdep *tdep;
  1182.   struct tdesc_arch_data *tdesc_data = NULL;
  1183.   const struct target_desc *tdesc = info.target_desc;
  1184.   int has_gp = 0;

  1186.   /* Check any target description for validity.  */
  1187.   if (tdesc_has_registers (tdesc))
  1188.     {
  1189.       const struct tdesc_feature *feature;
  1190.       int valid_p, i;

  1192.       feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core");

  1194.       if (feature == NULL)
  1195.         return NULL;

  1197.       tdesc_data = tdesc_data_alloc ();

  1199.       valid_p = 1;
  1200.       for (i = 0; i < 32; i++)        /* A0 - A15, B0 - B15 */
  1201.         valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
  1202.                                             tic6x_register_names[i]);

  1204.       /* CSR */
  1205.       valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
  1206.                                           tic6x_register_names[TIC6X_CSR_REGNUM]);
  1207.       valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
  1208.                                           tic6x_register_names[TIC6X_PC_REGNUM]);

  1210.       if (!valid_p)
  1211.         {
  1212.           tdesc_data_cleanup (tdesc_data);
  1213.           return NULL;
  1214.         }

  1216.       feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp");
  1217.       if (feature)
  1218.         {
  1219.           int j = 0;
  1220.           static const char *const gp[] =
  1221.             {
  1222.               "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
  1223.               "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
  1224.               "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
  1225.               "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
  1226.             };

  1228.           has_gp = 1;
  1229.           valid_p = 1;
  1230.           for (j = 0; j < 32; j++)        /* A16 - A31, B16 - B31 */
  1231.             valid_p &= tdesc_numbered_register (feature, tdesc_data, i++,
  1232.                                                 gp[j]);

  1234.           if (!valid_p)
  1235.             {
  1236.               tdesc_data_cleanup (tdesc_data);
  1237.               return NULL;
  1238.             }
  1239.         }

  1241.       feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp");
  1242.       if (feature)
  1243.         {
  1244.           valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR");
  1245.           valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC");
  1246.           valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC");

  1248.           if (!valid_p)
  1249.             {
  1250.               tdesc_data_cleanup (tdesc_data);
  1251.               return NULL;
  1252.             }
  1253.         }

  1255.     }

  1257.   /* Find a candidate among extant architectures.  */
  1258.   for (arches = gdbarch_list_lookup_by_info (arches, &info);
  1259.        arches != NULL;
  1260.        arches = gdbarch_list_lookup_by_info (arches->next, &info))
  1261.     {
  1262.       tdep = gdbarch_tdep (arches->gdbarch);

  1264.       if (has_gp != tdep->has_gp)
  1265.         continue;

  1267.       if (tdep && tdep->breakpoint)
  1268.         return arches->gdbarch;
  1269.     }

  1271.   tdep = xcalloc (1, sizeof (struct gdbarch_tdep));

  1273.   tdep->has_gp = has_gp;
  1274.   gdbarch = gdbarch_alloc (&info, tdep);

  1276.   /* Data type sizes.  */
  1277.   set_gdbarch_ptr_bit (gdbarch, 32);
  1278.   set_gdbarch_addr_bit (gdbarch, 32);
  1279.   set_gdbarch_short_bit (gdbarch, 16);
  1280.   set_gdbarch_int_bit (gdbarch, 32);
  1281.   set_gdbarch_long_bit (gdbarch, 32);
  1282.   set_gdbarch_long_long_bit (gdbarch, 64);
  1283.   set_gdbarch_float_bit (gdbarch, 32);
  1284.   set_gdbarch_double_bit (gdbarch, 64);

  1286.   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
  1287.   set_gdbarch_double_format (gdbarch, floatformats_ieee_double);

  1289.   /* The register set.  */
  1290.   set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS);
  1291.   set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM);
  1292.   set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM);

  1294.   set_gdbarch_register_name (gdbarch, tic6x_register_name);
  1295.   set_gdbarch_register_type (gdbarch, tic6x_register_type);

  1297.   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);

  1299.   set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue);
  1300.   set_gdbarch_breakpoint_from_pc (gdbarch, tic6x_breakpoint_from_pc);

  1302.   set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc);
  1303.   set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp);

  1305.   /* Unwinding.  */
  1306.   dwarf2_append_unwinders (gdbarch);

  1308.   frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind);
  1309.   frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind);
  1310.   frame_base_set_default (gdbarch, &tic6x_frame_base);

  1312.   dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg);

  1314.   /* Single stepping.  */
  1315.   set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step);

  1317.   set_gdbarch_print_insn (gdbarch, tic6x_print_insn);

  1319.   /* Call dummy code.  */
  1320.   set_gdbarch_frame_align (gdbarch, tic6x_frame_align);

  1322.   set_gdbarch_return_value (gdbarch, tic6x_return_value);

  1324.   set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id);

  1326.   /* Enable inferior call support.  */
  1327.   set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call);

  1329.   set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target);

  1331.   set_gdbarch_in_function_epilogue_p (gdbarch, tic6x_in_function_epilogue_p);

  1333.   set_gdbarch_return_in_first_hidden_param_p (gdbarch,
  1334.                                               tic6x_return_in_first_hidden_param_p);

  1336.   /* Hook in ABI-specific overrides, if they have been registered.  */
  1337.   gdbarch_init_osabi (info, gdbarch);

  1339.   if (tdesc_data)
  1340.     tdesc_use_registers (gdbarch, tdesc, tdesc_data);

  1342.   return gdbarch;
  1343. }

  1345. /* -Wmissing-prototypes */
  1346. extern initialize_file_ftype _initialize_tic6x_tdep;

  1348. void
  1349. ‌_initialize_tic6x_tdep (void)
  1350. {
  1351.   register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init);

  1353.   initialize_tdesc_tic6x_c64xp ();
  1354.   initialize_tdesc_tic6x_c64x ();
  1355.   initialize_tdesc_tic6x_c62x ();
  1356. }