gdb/rl78-tdep.c - gdb

Global variables defined

Data types defined

Functions defined

Source code

  1. /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.

  3.    Copyright (C) 2011-2015 Free Software Foundation, Inc.

  5.    Contributed by Red Hat, Inc.

  7.    This file is part of GDB.

  9.    This program is free software; you can redistribute it and/or modify
  10.    it under the terms of the GNU General Public License as published by
  11.    the Free Software Foundation; either version 3 of the License, or
  12.    (at your option) any later version.

  14.    This program is distributed in the hope that it will be useful,
  15.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17.    GNU General Public License for more details.

  19.    You should have received a copy of the GNU General Public License
  20.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  22. #include "defs.h"
  23. #include "arch-utils.h"
  24. #include "prologue-value.h"
  25. #include "target.h"
  26. #include "regcache.h"
  27. #include "opcode/rl78.h"
  28. #include "dis-asm.h"
  29. #include "gdbtypes.h"
  30. #include "frame.h"
  31. #include "frame-unwind.h"
  32. #include "frame-base.h"
  33. #include "value.h"
  34. #include "gdbcore.h"
  35. #include "dwarf2-frame.h"
  36. #include "reggroups.h"

  38. #include "elf/rl78.h"
  39. #include "elf-bfd.h"

  41. /* Register Banks.  */

  43. enum
  44. {
  45.   RL78_BANK0 = 0,
  46.   RL78_BANK1 = 1,
  47.   RL78_BANK2 = 2,
  48.   RL78_BANK3 = 3,
  49.   RL78_NUMBANKS = 4,
  50.   RL78_REGS_PER_BANK = 8
  51. };

  53. /* Register Numbers.  */

  55. enum
  56. {
  57.   /* All general purpose registers are 8 bits wide.  */
  58.   RL78_RAW_BANK0_R0_REGNUM = 0,
  59.   RL78_RAW_BANK0_R1_REGNUM,
  60.   RL78_RAW_BANK0_R2_REGNUM,
  61.   RL78_RAW_BANK0_R3_REGNUM,
  62.   RL78_RAW_BANK0_R4_REGNUM,
  63.   RL78_RAW_BANK0_R5_REGNUM,
  64.   RL78_RAW_BANK0_R6_REGNUM,
  65.   RL78_RAW_BANK0_R7_REGNUM,

  67.   RL78_RAW_BANK1_R0_REGNUM,
  68.   RL78_RAW_BANK1_R1_REGNUM,
  69.   RL78_RAW_BANK1_R2_REGNUM,
  70.   RL78_RAW_BANK1_R3_REGNUM,
  71.   RL78_RAW_BANK1_R4_REGNUM,
  72.   RL78_RAW_BANK1_R5_REGNUM,
  73.   RL78_RAW_BANK1_R6_REGNUM,
  74.   RL78_RAW_BANK1_R7_REGNUM,

  76.   RL78_RAW_BANK2_R0_REGNUM,
  77.   RL78_RAW_BANK2_R1_REGNUM,
  78.   RL78_RAW_BANK2_R2_REGNUM,
  79.   RL78_RAW_BANK2_R3_REGNUM,
  80.   RL78_RAW_BANK2_R4_REGNUM,
  81.   RL78_RAW_BANK2_R5_REGNUM,
  82.   RL78_RAW_BANK2_R6_REGNUM,
  83.   RL78_RAW_BANK2_R7_REGNUM,

  85.   RL78_RAW_BANK3_R0_REGNUM,
  86.   RL78_RAW_BANK3_R1_REGNUM,
  87.   RL78_RAW_BANK3_R2_REGNUM,
  88.   RL78_RAW_BANK3_R3_REGNUM,
  89.   RL78_RAW_BANK3_R4_REGNUM,
  90.   RL78_RAW_BANK3_R5_REGNUM,
  91.   RL78_RAW_BANK3_R6_REGNUM,
  92.   RL78_RAW_BANK3_R7_REGNUM,

  94.   RL78_PSW_REGNUM,        /* 8 bits */
  95.   RL78_ES_REGNUM,        /* 8 bits */
  96.   RL78_CS_REGNUM,        /* 8 bits */
  97.   RL78_RAW_PC_REGNUM,        /* 20 bits; we'll use 32 bits for it.  */

  99.   /* Fixed address SFRs (some of those above are SFRs too.) */
  100.   RL78_SPL_REGNUM,        /* 8 bits; lower half of SP */
  101.   RL78_SPH_REGNUM,        /* 8 bits; upper half of SP */
  102.   RL78_PMC_REGNUM,        /* 8 bits */
  103.   RL78_MEM_REGNUM,        /* 8 bits ?? */

  105.   RL78_NUM_REGS,

  107.   /* Pseudo registers.  */
  108.   RL78_PC_REGNUM = RL78_NUM_REGS,
  109.   RL78_SP_REGNUM,

  111.   RL78_X_REGNUM,
  112.   RL78_A_REGNUM,
  113.   RL78_C_REGNUM,
  114.   RL78_B_REGNUM,
  115.   RL78_E_REGNUM,
  116.   RL78_D_REGNUM,
  117.   RL78_L_REGNUM,
  118.   RL78_H_REGNUM,

  120.   RL78_AX_REGNUM,
  121.   RL78_BC_REGNUM,
  122.   RL78_DE_REGNUM,
  123.   RL78_HL_REGNUM,

  125.   RL78_BANK0_R0_REGNUM,
  126.   RL78_BANK0_R1_REGNUM,
  127.   RL78_BANK0_R2_REGNUM,
  128.   RL78_BANK0_R3_REGNUM,
  129.   RL78_BANK0_R4_REGNUM,
  130.   RL78_BANK0_R5_REGNUM,
  131.   RL78_BANK0_R6_REGNUM,
  132.   RL78_BANK0_R7_REGNUM,

  134.   RL78_BANK1_R0_REGNUM,
  135.   RL78_BANK1_R1_REGNUM,
  136.   RL78_BANK1_R2_REGNUM,
  137.   RL78_BANK1_R3_REGNUM,
  138.   RL78_BANK1_R4_REGNUM,
  139.   RL78_BANK1_R5_REGNUM,
  140.   RL78_BANK1_R6_REGNUM,
  141.   RL78_BANK1_R7_REGNUM,

  143.   RL78_BANK2_R0_REGNUM,
  144.   RL78_BANK2_R1_REGNUM,
  145.   RL78_BANK2_R2_REGNUM,
  146.   RL78_BANK2_R3_REGNUM,
  147.   RL78_BANK2_R4_REGNUM,
  148.   RL78_BANK2_R5_REGNUM,
  149.   RL78_BANK2_R6_REGNUM,
  150.   RL78_BANK2_R7_REGNUM,

  152.   RL78_BANK3_R0_REGNUM,
  153.   RL78_BANK3_R1_REGNUM,
  154.   RL78_BANK3_R2_REGNUM,
  155.   RL78_BANK3_R3_REGNUM,
  156.   RL78_BANK3_R4_REGNUM,
  157.   RL78_BANK3_R5_REGNUM,
  158.   RL78_BANK3_R6_REGNUM,
  159.   RL78_BANK3_R7_REGNUM,

  161.   RL78_BANK0_RP0_REGNUM,
  162.   RL78_BANK0_RP1_REGNUM,
  163.   RL78_BANK0_RP2_REGNUM,
  164.   RL78_BANK0_RP3_REGNUM,

  166.   RL78_BANK1_RP0_REGNUM,
  167.   RL78_BANK1_RP1_REGNUM,
  168.   RL78_BANK1_RP2_REGNUM,
  169.   RL78_BANK1_RP3_REGNUM,

  171.   RL78_BANK2_RP0_REGNUM,
  172.   RL78_BANK2_RP1_REGNUM,
  173.   RL78_BANK2_RP2_REGNUM,
  174.   RL78_BANK2_RP3_REGNUM,

  176.   RL78_BANK3_RP0_REGNUM,
  177.   RL78_BANK3_RP1_REGNUM,
  178.   RL78_BANK3_RP2_REGNUM,
  179.   RL78_BANK3_RP3_REGNUM,

  181.   /* These are the same as the above 16 registers, but have
  182.      a pointer type for use as base registers in expression
  183.      evaluation.  These are not user visible registers.  */
  184.   RL78_BANK0_RP0_PTR_REGNUM,
  185.   RL78_BANK0_RP1_PTR_REGNUM,
  186.   RL78_BANK0_RP2_PTR_REGNUM,
  187.   RL78_BANK0_RP3_PTR_REGNUM,

  189.   RL78_BANK1_RP0_PTR_REGNUM,
  190.   RL78_BANK1_RP1_PTR_REGNUM,
  191.   RL78_BANK1_RP2_PTR_REGNUM,
  192.   RL78_BANK1_RP3_PTR_REGNUM,

  194.   RL78_BANK2_RP0_PTR_REGNUM,
  195.   RL78_BANK2_RP1_PTR_REGNUM,
  196.   RL78_BANK2_RP2_PTR_REGNUM,
  197.   RL78_BANK2_RP3_PTR_REGNUM,

  199.   RL78_BANK3_RP0_PTR_REGNUM,
  200.   RL78_BANK3_RP1_PTR_REGNUM,
  201.   RL78_BANK3_RP2_PTR_REGNUM,
  202.   RL78_BANK3_RP3_PTR_REGNUM,

  204.   RL78_NUM_TOTAL_REGS,
  205.   RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
  206. };

  208. /* Architecture specific data.  */

  210. ‌struct gdbarch_tdep
  211. {
  212.   /* The ELF header flags specify the multilib used.  */
  213.   int elf_flags;

  215.   struct type *rl78_void,
  216.               *rl78_uint8,
  217.               *rl78_int8,
  218.               *rl78_uint16,
  219.               *rl78_int16,
  220.               *rl78_uint32,
  221.               *rl78_int32,
  222.               *rl78_data_pointer,
  223.               *rl78_code_pointer;
  224. };

  226. /* This structure holds the results of a prologue analysis.  */

  228. ‌struct rl78_prologue
  229. {
  230.   /* The offset from the frame base to the stack pointer --- always
  231.      zero or negative.

  233.      Calling this a "size" is a bit misleading, but given that the
  234.      stack grows downwards, using offsets for everything keeps one
  235.      from going completely sign-crazy: you never change anything's
  236.      sign for an ADD instruction; always change the second operand's
  237.      sign for a SUB instruction; and everything takes care of
  238.      itself.  */
  239.   int frame_size;

  241.   /* Non-zero if this function has initialized the frame pointer from
  242.      the stack pointer, zero otherwise.  */
  243.   int has_frame_ptr;

  245.   /* If has_frame_ptr is non-zero, this is the offset from the frame
  246.      base to where the frame pointer points.  This is always zero or
  247.      negative.  */
  248.   int frame_ptr_offset;

  250.   /* The address of the first instruction at which the frame has been
  251.      set up and the arguments are where the debug info says they are
  252.      --- as best as we can tell.  */
  253.   CORE_ADDR prologue_end;

  255.   /* reg_offset[R] is the offset from the CFA at which register R is
  256.      saved, or 1 if register R has not been saved.  (Real values are
  257.      always zero or negative.)  */
  258.   int reg_offset[RL78_NUM_TOTAL_REGS];
  259. };

  261. /* Implement the "register_type" gdbarch method.  */

  263. static struct type *
  264. ‌rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
  265. {
  266.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  268.   if (reg_nr == RL78_PC_REGNUM)
  269.     return tdep->rl78_code_pointer;
  270.   else if (reg_nr == RL78_RAW_PC_REGNUM)
  271.     return tdep->rl78_uint32;
  272.   else if (reg_nr <= RL78_MEM_REGNUM
  273.            || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
  274.            || (RL78_BANK0_R0_REGNUM <= reg_nr
  275.                && reg_nr <= RL78_BANK3_R7_REGNUM))
  276.     return tdep->rl78_int8;
  277.   else if (reg_nr == RL78_SP_REGNUM
  278.            || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
  279.                && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
  280.     return tdep->rl78_data_pointer;
  281.   else
  282.     return tdep->rl78_int16;
  283. }

  285. /* Implement the "register_name" gdbarch method.  */

  287. static const char *
  288. ‌rl78_register_name (struct gdbarch *gdbarch, int regnr)
  289. {
  290.   static const char *const reg_names[] =
  291.   {
  292.     "",                /* bank0_r0 */
  293.     "",                /* bank0_r1 */
  294.     "",                /* bank0_r2 */
  295.     "",                /* bank0_r3 */
  296.     "",                /* bank0_r4 */
  297.     "",                /* bank0_r5 */
  298.     "",                /* bank0_r6 */
  299.     "",                /* bank0_r7 */

  301.     "",                /* bank1_r0 */
  302.     "",                /* bank1_r1 */
  303.     "",                /* bank1_r2 */
  304.     "",                /* bank1_r3 */
  305.     "",                /* bank1_r4 */
  306.     "",                /* bank1_r5 */
  307.     "",                /* bank1_r6 */
  308.     "",                /* bank1_r7 */

  310.     "",                /* bank2_r0 */
  311.     "",                /* bank2_r1 */
  312.     "",                /* bank2_r2 */
  313.     "",                /* bank2_r3 */
  314.     "",                /* bank2_r4 */
  315.     "",                /* bank2_r5 */
  316.     "",                /* bank2_r6 */
  317.     "",                /* bank2_r7 */

  319.     "",                /* bank3_r0 */
  320.     "",                /* bank3_r1 */
  321.     "",                /* bank3_r2 */
  322.     "",                /* bank3_r3 */
  323.     "",                /* bank3_r4 */
  324.     "",                /* bank3_r5 */
  325.     "",                /* bank3_r6 */
  326.     "",                /* bank3_r7 */

  328.     "psw",
  329.     "es",
  330.     "cs",
  331.     "",

  333.     "",                /* spl */
  334.     "",                /* sph */
  335.     "pmc",
  336.     "mem",

  338.     "pc",
  339.     "sp",

  341.     "x",
  342.     "a",
  343.     "c",
  344.     "b",
  345.     "e",
  346.     "d",
  347.     "l",
  348.     "h",

  350.     "ax",
  351.     "bc",
  352.     "de",
  353.     "hl",

  355.     "bank0_r0",
  356.     "bank0_r1",
  357.     "bank0_r2",
  358.     "bank0_r3",
  359.     "bank0_r4",
  360.     "bank0_r5",
  361.     "bank0_r6",
  362.     "bank0_r7",

  364.     "bank1_r0",
  365.     "bank1_r1",
  366.     "bank1_r2",
  367.     "bank1_r3",
  368.     "bank1_r4",
  369.     "bank1_r5",
  370.     "bank1_r6",
  371.     "bank1_r7",

  373.     "bank2_r0",
  374.     "bank2_r1",
  375.     "bank2_r2",
  376.     "bank2_r3",
  377.     "bank2_r4",
  378.     "bank2_r5",
  379.     "bank2_r6",
  380.     "bank2_r7",

  382.     "bank3_r0",
  383.     "bank3_r1",
  384.     "bank3_r2",
  385.     "bank3_r3",
  386.     "bank3_r4",
  387.     "bank3_r5",
  388.     "bank3_r6",
  389.     "bank3_r7",

  391.     "bank0_rp0",
  392.     "bank0_rp1",
  393.     "bank0_rp2",
  394.     "bank0_rp3",

  396.     "bank1_rp0",
  397.     "bank1_rp1",
  398.     "bank1_rp2",
  399.     "bank1_rp3",

  401.     "bank2_rp0",
  402.     "bank2_rp1",
  403.     "bank2_rp2",
  404.     "bank2_rp3",

  406.     "bank3_rp0",
  407.     "bank3_rp1",
  408.     "bank3_rp2",
  409.     "bank3_rp3",

  411.     /* The 16 register slots would be named
  412.        bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
  413.        want these to be user visible registers.  */
  414.     "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
  415.   };

  417.   return reg_names[regnr];
  418. }

  420. /* Implement the "register_name" gdbarch method for the g10 variant.  */

  422. static const char *
  423. ‌rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
  424. {
  425.   static const char *const reg_names[] =
  426.   {
  427.     "",                /* bank0_r0 */
  428.     "",                /* bank0_r1 */
  429.     "",                /* bank0_r2 */
  430.     "",                /* bank0_r3 */
  431.     "",                /* bank0_r4 */
  432.     "",                /* bank0_r5 */
  433.     "",                /* bank0_r6 */
  434.     "",                /* bank0_r7 */

  436.     "",                /* bank1_r0 */
  437.     "",                /* bank1_r1 */
  438.     "",                /* bank1_r2 */
  439.     "",                /* bank1_r3 */
  440.     "",                /* bank1_r4 */
  441.     "",                /* bank1_r5 */
  442.     "",                /* bank1_r6 */
  443.     "",                /* bank1_r7 */

  445.     "",                /* bank2_r0 */
  446.     "",                /* bank2_r1 */
  447.     "",                /* bank2_r2 */
  448.     "",                /* bank2_r3 */
  449.     "",                /* bank2_r4 */
  450.     "",                /* bank2_r5 */
  451.     "",                /* bank2_r6 */
  452.     "",                /* bank2_r7 */

  454.     "",                /* bank3_r0 */
  455.     "",                /* bank3_r1 */
  456.     "",                /* bank3_r2 */
  457.     "",                /* bank3_r3 */
  458.     "",                /* bank3_r4 */
  459.     "",                /* bank3_r5 */
  460.     "",                /* bank3_r6 */
  461.     "",                /* bank3_r7 */

  463.     "psw",
  464.     "es",
  465.     "cs",
  466.     "",

  468.     "",                /* spl */
  469.     "",                /* sph */
  470.     "pmc",
  471.     "mem",

  473.     "pc",
  474.     "sp",

  476.     "x",
  477.     "a",
  478.     "c",
  479.     "b",
  480.     "e",
  481.     "d",
  482.     "l",
  483.     "h",

  485.     "ax",
  486.     "bc",
  487.     "de",
  488.     "hl",

  490.     "bank0_r0",
  491.     "bank0_r1",
  492.     "bank0_r2",
  493.     "bank0_r3",
  494.     "bank0_r4",
  495.     "bank0_r5",
  496.     "bank0_r6",
  497.     "bank0_r7",

  499.     "",
  500.     "",
  501.     "",
  502.     "",
  503.     "",
  504.     "",
  505.     "",
  506.     "",

  508.     "",
  509.     "",
  510.     "",
  511.     "",
  512.     "",
  513.     "",
  514.     "",
  515.     "",

  517.     "",
  518.     "",
  519.     "",
  520.     "",
  521.     "",
  522.     "",
  523.     "",
  524.     "",

  526.     "bank0_rp0",
  527.     "bank0_rp1",
  528.     "bank0_rp2",
  529.     "bank0_rp3",

  531.     "",
  532.     "",
  533.     "",
  534.     "",

  536.     "",
  537.     "",
  538.     "",
  539.     "",

  541.     "",
  542.     "",
  543.     "",
  544.     "",

  546.     /* The 16 register slots would be named
  547.        bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
  548.        want these to be user visible registers.  */
  549.     "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
  550.   };

  552.   return reg_names[regnr];
  553. }

  555. /* Implement the "register_reggroup_p" gdbarch method.  */

  557. static int
  558. ‌rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  559.                           struct reggroup *group)
  560. {
  561.   if (group == all_reggroup)
  562.     return 1;

  564.   /* All other registers are saved and restored.  */
  565.   if (group == save_reggroup || group == restore_reggroup)
  566.     {
  567.       if ((regnum < RL78_NUM_REGS
  568.            && regnum != RL78_SPL_REGNUM
  569.            && regnum != RL78_SPH_REGNUM
  570.            && regnum != RL78_RAW_PC_REGNUM)
  571.           || regnum == RL78_SP_REGNUM
  572.           || regnum == RL78_PC_REGNUM)
  573.         return 1;
  574.       else
  575.         return 0;
  576.     }

  578.   if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
  579.       || regnum == RL78_ES_REGNUM
  580.       || regnum == RL78_CS_REGNUM
  581.       || regnum == RL78_SPL_REGNUM
  582.       || regnum == RL78_SPH_REGNUM
  583.       || regnum == RL78_PMC_REGNUM
  584.       || regnum == RL78_MEM_REGNUM
  585.       || regnum == RL78_RAW_PC_REGNUM
  586.       || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
  587.     return group == system_reggroup;

  589.   return group == general_reggroup;
  590. }

  592. /* Strip bits to form an instruction address.  (When fetching a
  593.    32-bit address from the stack, the high eight bits are garbage.
  594.    This function strips off those unused bits.)  */

  596. static CORE_ADDR
  597. ‌rl78_make_instruction_address (CORE_ADDR addr)
  598. {
  599.   return addr & 0xffffff;
  600. }

  602. /* Set / clear bits necessary to make a data address.  */

  604. static CORE_ADDR
  605. ‌rl78_make_data_address (CORE_ADDR addr)
  606. {
  607.   return (addr & 0xffff) | 0xf0000;
  608. }

  610. /* Implement the "pseudo_register_read" gdbarch method.  */

  612. static enum register_status
  613. ‌rl78_pseudo_register_read (struct gdbarch *gdbarch,
  614.                            struct regcache *regcache,
  615.                            int reg, gdb_byte *buffer)
  616. {
  617.   enum register_status status;

  619.   if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
  620.     {
  621.       int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
  622.                        + (reg - RL78_BANK0_R0_REGNUM);

  624.       status = regcache_raw_read (regcache, raw_regnum, buffer);
  625.     }
  626.   else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
  627.     {
  628.       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
  629.                        + RL78_RAW_BANK0_R0_REGNUM;

  631.       status = regcache_raw_read (regcache, raw_regnum, buffer);
  632.       if (status == REG_VALID)
  633.         status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
  634.     }
  635.   else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
  636.     {
  637.       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
  638.                        + RL78_RAW_BANK0_R0_REGNUM;

  640.       status = regcache_raw_read (regcache, raw_regnum, buffer);
  641.       if (status == REG_VALID)
  642.         status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
  643.     }
  644.   else if (reg == RL78_SP_REGNUM)
  645.     {
  646.       status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
  647.       if (status == REG_VALID)
  648.         status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
  649.     }
  650.   else if (reg == RL78_PC_REGNUM)
  651.     {
  652.       gdb_byte rawbuf[4];

  654.       status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
  655.       memcpy (buffer, rawbuf, 3);
  656.     }
  657.   else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
  658.     {
  659.       ULONGEST psw;

  661.       status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
  662.       if (status == REG_VALID)
  663.         {
  664.           /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
  665.           int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
  666.           int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
  667.                            + (reg - RL78_X_REGNUM);
  668.           status = regcache_raw_read (regcache, raw_regnum, buffer);
  669.         }
  670.     }
  671.   else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
  672.     {
  673.       ULONGEST psw;

  675.       status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
  676.       if (status == REG_VALID)
  677.         {
  678.           /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
  679.           int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
  680.           int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
  681.                            + 2 * (reg - RL78_AX_REGNUM);
  682.           status = regcache_raw_read (regcache, raw_regnum, buffer);
  683.           if (status == REG_VALID)
  684.             status = regcache_raw_read (regcache, raw_regnum + 1,
  685.                                         buffer + 1);
  686.         }
  687.     }
  688.   else
  689.     gdb_assert_not_reached ("invalid pseudo register number");
  690.   return status;
  691. }

  693. /* Implement the "pseudo_register_write" gdbarch method.  */

  695. static void
  696. ‌rl78_pseudo_register_write (struct gdbarch *gdbarch,
  697.                             struct regcache *regcache,
  698.                             int reg, const gdb_byte *buffer)
  699. {
  700.   if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
  701.     {
  702.       int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
  703.                        + (reg - RL78_BANK0_R0_REGNUM);

  705.       regcache_raw_write (regcache, raw_regnum, buffer);
  706.     }
  707.   else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
  708.     {
  709.       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
  710.                        + RL78_RAW_BANK0_R0_REGNUM;

  712.       regcache_raw_write (regcache, raw_regnum, buffer);
  713.       regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
  714.     }
  715.   else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
  716.     {
  717.       int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
  718.                        + RL78_RAW_BANK0_R0_REGNUM;

  720.       regcache_raw_write (regcache, raw_regnum, buffer);
  721.       regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
  722.     }
  723.   else if (reg == RL78_SP_REGNUM)
  724.     {
  725.       regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
  726.       regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
  727.     }
  728.   else if (reg == RL78_PC_REGNUM)
  729.     {
  730.       gdb_byte rawbuf[4];

  732.       memcpy (rawbuf, buffer, 3);
  733.       rawbuf[3] = 0;
  734.       regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
  735.     }
  736.   else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
  737.     {
  738.       ULONGEST psw;
  739.       int bank;
  740.       int raw_regnum;

  742.       regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
  743.       bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
  744.       /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
  745.       raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
  746.                    + (reg - RL78_X_REGNUM);
  747.       regcache_raw_write (regcache, raw_regnum, buffer);
  748.     }
  749.   else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
  750.     {
  751.       ULONGEST psw;
  752.       int bank, raw_regnum;

  754.       regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
  755.       bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
  756.       /* RSB0 is at bit 3; RSBS1 is at bit 5.  */
  757.       raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
  758.                    + 2 * (reg - RL78_AX_REGNUM);
  759.       regcache_raw_write (regcache, raw_regnum, buffer);
  760.       regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
  761.     }
  762.   else
  763.     gdb_assert_not_reached ("invalid pseudo register number");
  764. }

  766. /* Implement the "breakpoint_from_pc" gdbarch method.  */

  768. static const gdb_byte *
  769. ‌rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
  770.                          int *lenptr)
  771. {
  772.   /* The documented BRK instruction is actually a two byte sequence,
  773.      {0x61, 0xcc}, but instructions may be as short as one byte.
  774.      Correspondence with Renesas revealed that the one byte sequence
  775.      0xff is used when a one byte breakpoint instruction is required.  */
  776.   static gdb_byte breakpoint[] = { 0xff };

  778.   *lenptr = sizeof breakpoint;
  779.   return breakpoint;
  780. }

  782. /* Define a "handle" struct for fetching the next opcode.  */

  784. ‌struct rl78_get_opcode_byte_handle
  785. {
  786.   CORE_ADDR pc;
  787. };

  789. /* Fetch a byte on behalf of the opcode decoder.  HANDLE contains
  790.    the memory address of the next byte to fetch.  If successful,
  791.    the address in the handle is updated and the byte fetched is
  792.    returned as the value of the function.  If not successful, -1
  793.    is returned.  */

  795. static int
  796. ‌rl78_get_opcode_byte (void *handle)
  797. {
  798.   struct rl78_get_opcode_byte_handle *opcdata = handle;
  799.   int status;
  800.   gdb_byte byte;

  802.   status = target_read_memory (opcdata->pc, &byte, 1);
  803.   if (status == 0)
  804.     {
  805.       opcdata->pc += 1;
  806.       return byte;
  807.     }
  808.   else
  809.     return -1;
  810. }

  812. /* Function for finding saved registers in a 'struct pv_area'; this
  813.    function is passed to pv_area_scan.

  815.    If VALUE is a saved register, ADDR says it was saved at a constant
  816.    offset from the frame base, and SIZE indicates that the whole
  817.    register was saved, record its offset.  */

  819. static void
  820. ‌check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
  821.                  pv_t value)
  822. {
  823.   struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;

  825.   if (value.kind == pvk_register
  826.       && value.k == 0
  827.       && pv_is_register (addr, RL78_SP_REGNUM)
  828.       && size == register_size (target_gdbarch (), value.reg))
  829.     result->reg_offset[value.reg] = addr.k;
  830. }

  832. /* Analyze a prologue starting at START_PC, going no further than
  833.    LIMIT_PC.  Fill in RESULT as appropriate.  */

  835. static void
  836. ‌rl78_analyze_prologue (CORE_ADDR start_pc,
  837.                        CORE_ADDR limit_pc, struct rl78_prologue *result)
  838. {
  839.   CORE_ADDR pc, next_pc;
  840.   int rn;
  841.   pv_t reg[RL78_NUM_TOTAL_REGS];
  842.   struct pv_area *stack;
  843.   struct cleanup *back_to;
  844.   CORE_ADDR after_last_frame_setup_insn = start_pc;
  845.   int bank = 0;

  847.   memset (result, 0, sizeof (*result));

  849.   for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
  850.     {
  851.       reg[rn] = pv_register (rn, 0);
  852.       result->reg_offset[rn] = 1;
  853.     }

  855.   stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
  856.   back_to = make_cleanup_free_pv_area (stack);

  858.   /* The call instruction has saved the return address on the stack.  */
  859.   reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
  860.   pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);

  862.   pc = start_pc;
  863.   while (pc < limit_pc)
  864.     {
  865.       int bytes_read;
  866.       struct rl78_get_opcode_byte_handle opcode_handle;
  867.       RL78_Opcode_Decoded opc;

  869.       opcode_handle.pc = pc;
  870.       bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
  871.                                      &opcode_handle);
  872.       next_pc = pc + bytes_read;

  874.       if (opc.id == RLO_sel)
  875.         {
  876.           bank = opc.op[1].addend;
  877.         }
  878.       else if (opc.id == RLO_mov
  879.                && opc.op[0].type == RL78_Operand_PreDec
  880.                && opc.op[0].reg == RL78_Reg_SP
  881.                && opc.op[1].type == RL78_Operand_Register)
  882.         {
  883.           int rsrc = (bank * RL78_REGS_PER_BANK)
  884.                    + 2 * (opc.op[1].reg - RL78_Reg_AX);

  886.           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
  887.           pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
  888.           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
  889.           pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
  890.           after_last_frame_setup_insn = next_pc;
  891.         }
  892.       else if (opc.id == RLO_sub
  893.                && opc.op[0].type == RL78_Operand_Register
  894.                && opc.op[0].reg == RL78_Reg_SP
  895.                && opc.op[1].type == RL78_Operand_Immediate)
  896.         {
  897.           int addend = opc.op[1].addend;

  899.           reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
  900.                                                  -addend);
  901.           after_last_frame_setup_insn = next_pc;
  902.         }
  903.       else
  904.         {
  905.           /* Terminate the prologue scan.  */
  906.           break;
  907.         }

  909.       pc = next_pc;
  910.     }

  912.   /* Is the frame size (offset, really) a known constant?  */
  913.   if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
  914.     result->frame_size = reg[RL78_SP_REGNUM].k;

  916.   /* Record where all the registers were saved.  */
  917.   pv_area_scan (stack, check_for_saved, (void *) result);

  919.   result->prologue_end = after_last_frame_setup_insn;

  921.   do_cleanups (back_to);
  922. }

  924. /* Implement the "addr_bits_remove" gdbarch method.  */

  926. static CORE_ADDR
  927. ‌rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
  928. {
  929.   return addr & 0xffffff;
  930. }

  932. /* Implement the "address_to_pointer" gdbarch method.  */

  934. static void
  935. ‌rl78_address_to_pointer (struct gdbarch *gdbarch,
  936.                          struct type *type, gdb_byte *buf, CORE_ADDR addr)
  937. {
  938.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);

  940.   store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
  941.                           addr & 0xffffff);
  942. }

  944. /* Implement the "pointer_to_address" gdbarch method.  */

  946. static CORE_ADDR
  947. ‌rl78_pointer_to_address (struct gdbarch *gdbarch,
  948.                          struct type *type, const gdb_byte *buf)
  949. {
  950.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  951.   CORE_ADDR addr
  952.     = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);

  954.   /* Is it a code address?  */
  955.   if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
  956.       || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
  957.       || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
  958.       || TYPE_LENGTH (type) == 4)
  959.     return rl78_make_instruction_address (addr);
  960.   else
  961.     return rl78_make_data_address (addr);
  962. }

  964. /* Implement the "skip_prologue" gdbarch method.  */

  966. static CORE_ADDR
  967. ‌rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  968. {
  969.   const char *name;
  970.   CORE_ADDR func_addr, func_end;
  971.   struct rl78_prologue p;

  973.   /* Try to find the extent of the function that contains PC.  */
  974.   if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
  975.     return pc;

  977.   rl78_analyze_prologue (pc, func_end, &p);
  978.   return p.prologue_end;
  979. }

  981. /* Implement the "unwind_pc" gdbarch method.  */

  983. static CORE_ADDR
  984. ‌rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
  985. {
  986.   return rl78_addr_bits_remove
  987.            (arch, frame_unwind_register_unsigned (next_frame,
  988.                                                   RL78_PC_REGNUM));
  989. }

  991. /* Implement the "unwind_sp" gdbarch method.  */

  993. static CORE_ADDR
  994. ‌rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
  995. {
  996.   return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
  997. }

  999. /* Given a frame described by THIS_FRAME, decode the prologue of its
  1000.    associated function if there is not cache entry as specified by
  1001.    THIS_PROLOGUE_CACHE.  Save the decoded prologue in the cache and
  1002.    return that struct as the value of this function.  */

  1004. static struct rl78_prologue *
  1005. ‌rl78_analyze_frame_prologue (struct frame_info *this_frame,
  1006.                            void **this_prologue_cache)
  1007. {
  1008.   if (!*this_prologue_cache)
  1009.     {
  1010.       CORE_ADDR func_start, stop_addr;

  1012.       *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);

  1014.       func_start = get_frame_func (this_frame);
  1015.       stop_addr = get_frame_pc (this_frame);

  1017.       /* If we couldn't find any function containing the PC, then
  1018.          just initialize the prologue cache, but don't do anything.  */
  1019.       if (!func_start)
  1020.         stop_addr = func_start;

  1022.       rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
  1023.     }

  1025.   return *this_prologue_cache;
  1026. }

  1028. /* Given a frame and a prologue cache, return this frame's base.  */

  1030. static CORE_ADDR
  1031. ‌rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
  1032. {
  1033.   struct rl78_prologue *p
  1034.     = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
  1035.   CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);

  1037.   return rl78_make_data_address (sp - p->frame_size);
  1038. }

  1040. /* Implement the "frame_this_id" method for unwinding frames.  */

  1042. static void
  1043. ‌rl78_this_id (struct frame_info *this_frame,
  1044.               void **this_prologue_cache, struct frame_id *this_id)
  1045. {
  1046.   *this_id = frame_id_build (rl78_frame_base (this_frame,
  1047.                                               this_prologue_cache),
  1048.                              get_frame_func (this_frame));
  1049. }

  1051. /* Implement the "frame_prev_register" method for unwinding frames.  */

  1053. static struct value *
  1054. ‌rl78_prev_register (struct frame_info *this_frame,
  1055.                     void **this_prologue_cache, int regnum)
  1056. {
  1057.   struct rl78_prologue *p
  1058.     = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
  1059.   CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);

  1061.   if (regnum == RL78_SP_REGNUM)
  1062.     return frame_unwind_got_constant (this_frame, regnum, frame_base);

  1064.   else if (regnum == RL78_SPL_REGNUM)
  1065.     return frame_unwind_got_constant (this_frame, regnum,
  1066.                                       (frame_base & 0xff));

  1068.   else if (regnum == RL78_SPH_REGNUM)
  1069.     return frame_unwind_got_constant (this_frame, regnum,
  1070.                                       ((frame_base >> 8) & 0xff));

  1072.   /* If prologue analysis says we saved this register somewhere,
  1073.      return a description of the stack slot holding it.  */
  1074.   else if (p->reg_offset[regnum] != 1)
  1075.     {
  1076.       struct value *rv =
  1077.         frame_unwind_got_memory (this_frame, regnum,
  1078.                                  frame_base + p->reg_offset[regnum]);

  1080.       if (regnum == RL78_PC_REGNUM)
  1081.         {
  1082.           ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));

  1084.           return frame_unwind_got_constant (this_frame, regnum, pc);
  1085.         }
  1086.       return rv;
  1087.     }

  1089.   /* Otherwise, presume we haven't changed the value of this
  1090.      register, and get it from the next frame.  */
  1091.   else
  1092.     return frame_unwind_got_register (this_frame, regnum, regnum);
  1093. }

  1095. ‌static const struct frame_unwind rl78_unwind =
  1096. {
  1097.   NORMAL_FRAME,
  1098.   default_frame_unwind_stop_reason,
  1099.   rl78_this_id,
  1100.   rl78_prev_register,
  1101.   NULL,
  1102.   default_frame_sniffer
  1103. };

  1105. /* Implement the "dwarf_reg_to_regnum" gdbarch method.  */

  1107. static int
  1108. ‌rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
  1109. {
  1110.   if (0 <= reg && reg <= 31)
  1111.     {
  1112.       if ((reg & 1) == 0)
  1113.         /* Map even registers to their 16-bit counterparts which have a
  1114.            pointer type.  This is usually what is required from the DWARF
  1115.            info.  */
  1116.         return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
  1117.       else
  1118.         return reg;
  1119.     }
  1120.   else if (reg == 32)
  1121.     return RL78_SP_REGNUM;
  1122.   else if (reg == 33)
  1123.     return -1;                        /* ap */
  1124.   else if (reg == 34)
  1125.     return RL78_PSW_REGNUM;
  1126.   else if (reg == 35)
  1127.     return RL78_ES_REGNUM;
  1128.   else if (reg == 36)
  1129.     return RL78_CS_REGNUM;
  1130.   else if (reg == 37)
  1131.     return RL78_PC_REGNUM;
  1132.   else
  1133.     internal_error (__FILE__, __LINE__,
  1134.                     _("Undefined dwarf2 register mapping of reg %d"),
  1135.                     reg);
  1136. }

  1138. /* Implement the `register_sim_regno' gdbarch method.  */

  1140. static int
  1141. ‌rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
  1142. {
  1143.   gdb_assert (regnum < RL78_NUM_REGS);

  1145.   /* So long as regnum is in [0, RL78_NUM_REGS), it's valid.  We
  1146.      just want to override the default here which disallows register
  1147.      numbers which have no names.  */
  1148.   return regnum;
  1149. }

  1151. /* Implement the "return_value" gdbarch method.  */

  1153. static enum return_value_convention
  1154. ‌rl78_return_value (struct gdbarch *gdbarch,
  1155.                    struct value *function,
  1156.                    struct type *valtype,
  1157.                    struct regcache *regcache,
  1158.                    gdb_byte *readbuf, const gdb_byte *writebuf)
  1159. {
  1160.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1161.   ULONGEST valtype_len = TYPE_LENGTH (valtype);
  1162.   int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;

  1164.   if (valtype_len > 8)
  1165.     return RETURN_VALUE_STRUCT_CONVENTION;

  1167.   if (readbuf)
  1168.     {
  1169.       ULONGEST u;
  1170.       int argreg = RL78_RAW_BANK1_R0_REGNUM;
  1171.       CORE_ADDR g10_raddr = 0xffec8;
  1172.       int offset = 0;

  1174.       while (valtype_len > 0)
  1175.         {
  1176.           if (is_g10)
  1177.             u = read_memory_integer (g10_raddr, 1,
  1178.                                      gdbarch_byte_order (gdbarch));
  1179.           else
  1180.             regcache_cooked_read_unsigned (regcache, argreg, &u);
  1181.           store_unsigned_integer (readbuf + offset, 1, byte_order, u);
  1182.           valtype_len -= 1;
  1183.           offset += 1;
  1184.           argreg++;
  1185.           g10_raddr++;
  1186.         }
  1187.     }

  1189.   if (writebuf)
  1190.     {
  1191.       ULONGEST u;
  1192.       int argreg = RL78_RAW_BANK1_R0_REGNUM;
  1193.       CORE_ADDR g10_raddr = 0xffec8;
  1194.       int offset = 0;

  1196.       while (valtype_len > 0)
  1197.         {
  1198.           u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
  1199.           if (is_g10) {
  1200.             gdb_byte b = u & 0xff;
  1201.             write_memory (g10_raddr, &b, 1);
  1202.           }
  1203.           else
  1204.             regcache_cooked_write_unsigned (regcache, argreg, u);
  1205.           valtype_len -= 1;
  1206.           offset += 1;
  1207.           argreg++;
  1208.           g10_raddr++;
  1209.         }
  1210.     }

  1212.   return RETURN_VALUE_REGISTER_CONVENTION;
  1213. }


  1216. /* Implement the "frame_align" gdbarch method.  */

  1218. static CORE_ADDR
  1219. ‌rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  1220. {
  1221.   return rl78_make_data_address (align_down (sp, 2));
  1222. }


  1225. /* Implement the "dummy_id" gdbarch method.  */

  1227. static struct frame_id
  1228. ‌rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
  1229. {
  1230.   return
  1231.     frame_id_build (rl78_make_data_address
  1232.                       (get_frame_register_unsigned
  1233.                         (this_frame, RL78_SP_REGNUM)),
  1234.                     get_frame_pc (this_frame));
  1235. }


  1238. /* Implement the "push_dummy_call" gdbarch method.  */

  1240. static CORE_ADDR
  1241. ‌rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
  1242.                       struct regcache *regcache, CORE_ADDR bp_addr,
  1243.                       int nargs, struct value **args, CORE_ADDR sp,
  1244.                       int struct_return, CORE_ADDR struct_addr)
  1245. {
  1246.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1247.   gdb_byte buf[4];
  1248.   int i;

  1250.   /* Push arguments in reverse order.  */
  1251.   for (i = nargs - 1; i >= 0; i--)
  1252.     {
  1253.       struct type *value_type = value_enclosing_type (args[i]);
  1254.       int len = TYPE_LENGTH (value_type);
  1255.       int container_len = (len + 1) & ~1;

  1257.       sp -= container_len;
  1258.       write_memory (rl78_make_data_address (sp),
  1259.                     value_contents_all (args[i]), len);
  1260.     }

  1262.   /* Store struct value address.  */
  1263.   if (struct_return)
  1264.     {
  1265.       store_unsigned_integer (buf, 2, byte_order, struct_addr);
  1266.       sp -= 2;
  1267.       write_memory (rl78_make_data_address (sp), buf, 2);
  1268.     }

  1270.   /* Store return address.  */
  1271.   sp -= 4;
  1272.   store_unsigned_integer (buf, 4, byte_order, bp_addr);
  1273.   write_memory (rl78_make_data_address (sp), buf, 4);

  1275.   /* Finally, update the stack pointer...  */
  1276.   regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);

  1278.   /* DWARF2/GCC uses the stack address *before* the function call as a
  1279.      frame's CFA.  */
  1280.   return rl78_make_data_address (sp + 4);
  1281. }

  1283. /* Allocate and initialize a gdbarch object.  */

  1285. static struct gdbarch *
  1286. ‌rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
  1287. {
  1288.   struct gdbarch *gdbarch;
  1289.   struct gdbarch_tdep *tdep;
  1290.   int elf_flags;

  1292.   /* Extract the elf_flags if available.  */
  1293.   if (info.abfd != NULL
  1294.       && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
  1295.     elf_flags = elf_elfheader (info.abfd)->e_flags;
  1296.   else
  1297.     elf_flags = 0;


  1300.   /* Try to find the architecture in the list of already defined
  1301.      architectures.  */
  1302.   for (arches = gdbarch_list_lookup_by_info (arches, &info);
  1303.        arches != NULL;
  1304.        arches = gdbarch_list_lookup_by_info (arches->next, &info))
  1305.     {
  1306.       if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
  1307.         continue;

  1309.       return arches->gdbarch;
  1310.     }

  1312.   /* None found, create a new architecture from the information
  1313.      provided.  */
  1314.   tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
  1315.   gdbarch = gdbarch_alloc (&info, tdep);
  1316.   tdep->elf_flags = elf_flags;

  1318.   /* Initialize types.  */
  1319.   tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
  1320.   tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
  1321.   tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
  1322.   tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
  1323.   tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
  1324.   tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
  1325.   tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");

  1327.   tdep->rl78_data_pointer
  1328.     = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
  1329.                  xstrdup ("rl78_data_addr_t"));
  1330.   TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
  1331.   TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;

  1333.   tdep->rl78_code_pointer
  1334.     = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
  1335.                  xstrdup ("rl78_code_addr_t"));
  1336.   TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
  1337.   TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;

  1339.   /* Registers.  */
  1340.   set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
  1341.   set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
  1342.   if (tdep->elf_flags & E_FLAG_RL78_G10)
  1343.     set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
  1344.   else
  1345.     set_gdbarch_register_name (gdbarch, rl78_register_name);
  1346.   set_gdbarch_register_type (gdbarch, rl78_register_type);
  1347.   set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
  1348.   set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
  1349.   set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
  1350.   set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
  1351.   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
  1352.   set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
  1353.   set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);

  1355.   /* Data types.  */
  1356.   set_gdbarch_char_signed (gdbarch, 0);
  1357.   set_gdbarch_short_bit (gdbarch, 16);
  1358.   set_gdbarch_int_bit (gdbarch, 16);
  1359.   set_gdbarch_long_bit (gdbarch, 32);
  1360.   set_gdbarch_long_long_bit (gdbarch, 64);
  1361.   set_gdbarch_ptr_bit (gdbarch, 16);
  1362.   set_gdbarch_addr_bit (gdbarch, 32);
  1363.   set_gdbarch_dwarf2_addr_size (gdbarch, 4);
  1364.   set_gdbarch_float_bit (gdbarch, 32);
  1365.   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
  1366.   set_gdbarch_double_bit (gdbarch, 32);
  1367.   set_gdbarch_long_double_bit (gdbarch, 64);
  1368.   set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
  1369.   set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
  1370.   set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
  1371.   set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
  1372.   set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);

  1374.   /* Breakpoints.  */
  1375.   set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
  1376.   set_gdbarch_decr_pc_after_break (gdbarch, 1);

  1378.   /* Disassembly.  */
  1379.   set_gdbarch_print_insn (gdbarch, print_insn_rl78);

  1381.   /* Frames, prologues, etc.  */
  1382.   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
  1383.   set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
  1384.   set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
  1385.   set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
  1386.   set_gdbarch_frame_align (gdbarch, rl78_frame_align);

  1388.   dwarf2_append_unwinders (gdbarch);
  1389.   frame_unwind_append_unwinder (gdbarch, &rl78_unwind);

  1391.   /* Dummy frames, return values.  */
  1392.   set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
  1393.   set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
  1394.   set_gdbarch_return_value (gdbarch, rl78_return_value);

  1396.   /* Virtual tables.  */
  1397.   set_gdbarch_vbit_in_delta (gdbarch, 1);

  1399.   return gdbarch;
  1400. }

  1402. /* -Wmissing-prototypes */
  1403. extern initialize_file_ftype _initialize_rl78_tdep;

  1405. /* Register the above initialization routine.  */

  1407. void
  1408. ‌_initialize_rl78_tdep (void)
  1409. {
  1410.   register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
  1411. }