gdb/gdbserver/linux-mips-low.c - gdb

Global variables defined

Data types defined

Functions defined

Macros defined

Source code

  1. /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
  2.    Copyright (C) 1995-2015 Free Software Foundation, Inc.

  4.    This file is part of GDB.

  6.    This program is free software; you can redistribute it and/or modify
  7.    it under the terms of the GNU General Public License as published by
  8.    the Free Software Foundation; either version 3 of the License, or
  9.    (at your option) any later version.

  11.    This program is distributed in the hope that it will be useful,
  12.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14.    GNU General Public License for more details.

  16.    You should have received a copy of the GNU General Public License
  17.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  19. #include "server.h"
  20. #include "linux-low.h"

  22. #include <sys/ptrace.h>
  23. #include <endian.h>

  25. #include "nat/mips-linux-watch.h"
  26. #include "gdb_proc_service.h"

  28. /* Defined in auto-generated file mips-linux.c.  */
  29. void init_registers_mips_linux (void);
  30. extern const struct target_desc *tdesc_mips_linux;

  32. /* Defined in auto-generated file mips-dsp-linux.c.  */
  33. void init_registers_mips_dsp_linux (void);
  34. extern const struct target_desc *tdesc_mips_dsp_linux;

  36. /* Defined in auto-generated file mips64-linux.c.  */
  37. void init_registers_mips64_linux (void);
  38. extern const struct target_desc *tdesc_mips64_linux;

  40. /* Defined in auto-generated file mips64-dsp-linux.c.  */
  41. void init_registers_mips64_dsp_linux (void);
  42. extern const struct target_desc *tdesc_mips64_dsp_linux;

  44. #ifdef __mips64
  45. ‌#define tdesc_mips_linux tdesc_mips64_linux
  46. ‌#define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  47. #endif

  49. #ifndef PTRACE_GET_THREAD_AREA
  50. ‌#define PTRACE_GET_THREAD_AREA 25
  51. #endif

  53. #ifdef HAVE_SYS_REG_H
  54. #include <sys/reg.h>
  55. #endif

  57. ‌#define mips_num_regs 73
  58. ‌#define mips_dsp_num_regs 80

  60. #include <asm/ptrace.h>

  62. #ifndef DSP_BASE
  63. ‌#define DSP_BASE 71
  64. ‌#define DSP_CONTROL 77
  65. #endif

  67. ‌union mips_register
  68. {
  69.   unsigned char buf[8];

  71.   /* Deliberately signed, for proper sign extension.  */
  72.   int reg32;
  73.   long long reg64;
  74. };

  76. /* Return the ptrace ``address'' of register REGNO. */

  78. ‌#define mips_base_regs                                                        \
  79.   -1,  1,  2,  3,  4,  5,  6,  7,                                        \
  80.   8,  9,  10, 11, 12, 13, 14, 15,                                        \
  81.   16, 17, 18, 19, 20, 21, 22, 23,                                        \
  82.   24, 25, 26, 27, 28, 29, 30, 31,                                        \
  83.                                                                         \
  84.   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                        \
  85.                                                                         \
  86.   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,                \
  87.   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,                \
  88.   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,                \
  89.   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,                \
  90.   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,                \
  91.   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,                \
  92.   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,                \
  93.   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,                \
  94.   FPC_CSR, FPC_EIR

  96. ‌#define mips_dsp_regs                                                        \
  97.   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,                \
  98.   DSP_BASE + 4,  DSP_BASE + 5,                                                \
  99.   DSP_CONTROL

  101. ‌static int mips_regmap[mips_num_regs] = {
  102.   mips_base_regs,
  103.   0
  104. };

  106. ‌static int mips_dsp_regmap[mips_dsp_num_regs] = {
  107.   mips_base_regs,
  108.   mips_dsp_regs,
  109.   0
  110. };

  112. /* DSP registers are not in any regset and can only be accessed
  113.    individually.  */

  115. ‌static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
  116.   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
  117. };

  119. ‌static int have_dsp = -1;

  121. /* Try peeking at an arbitrarily chosen DSP register and pick the available
  122.    user register set accordingly.  */

  124. static const struct target_desc *
  125. ‌mips_read_description (void)
  126. {
  127.   if (have_dsp < 0)
  128.     {
  129.       int pid = lwpid_of (current_thread);

  131.       errno = 0;
  132.       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
  133.       switch (errno)
  134.         {
  135.         case 0:
  136.           have_dsp = 1;
  137.           break;
  138.         case EIO:
  139.           have_dsp = 0;
  140.           break;
  141.         default:
  142.           perror_with_name ("ptrace");
  143.           break;
  144.         }
  145.     }

  147.   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
  148. }

  150. static void
  151. ‌mips_arch_setup (void)
  152. {
  153.   current_process ()->tdesc = mips_read_description ();
  154. }

  156. static struct usrregs_info *
  157. ‌get_usrregs_info (void)
  158. {
  159.   const struct regs_info *regs_info = the_low_target.regs_info ();

  161.   return regs_info->usrregs;
  162. }

  164. /* Per-process arch-specific data we want to keep.  */

  166. ‌struct arch_process_info
  167. {
  168.   /* -1 if the kernel and/or CPU do not support watch registers.
  169.       1 if watch_readback is valid and we can read style, num_valid
  170.         and the masks.
  171.       0 if we need to read the watch_readback.  */

  173.   int watch_readback_valid;

  175.   /* Cached watch register read values.  */

  177.   struct pt_watch_regs watch_readback;

  179.   /* Current watchpoint requests for this process.  */

  181.   struct mips_watchpoint *current_watches;

  183.   /* The current set of watch register values for writing the
  184.      registers.  */

  186.   struct pt_watch_regs watch_mirror;
  187. };

  189. /* Per-thread arch-specific data we want to keep.  */

  191. ‌struct arch_lwp_info
  192. {
  193.   /* Non-zero if our copy differs from what's recorded in the thread.  */
  194.   int watch_registers_changed;
  195. };

  197. /* From mips-linux-nat.c.  */

  199. /* Pseudo registers can not be read.  ptrace does not provide a way to
  200.    read (or set) PS_REGNUM, and there's no point in reading or setting
  201.    ZERO_REGNUM.  We also can not set BADVADDR, CAUSE, or FCRIR via
  202.    ptrace().  */

  204. static int
  205. ‌mips_cannot_fetch_register (int regno)
  206. {
  207.   const struct target_desc *tdesc;

  209.   if (get_usrregs_info ()->regmap[regno] == -1)
  210.     return 1;

  212.   tdesc = current_process ()->tdesc;

  214.   if (find_regno (tdesc, "r0") == regno)
  215.     return 1;

  217.   return 0;
  218. }

  220. static int
  221. ‌mips_cannot_store_register (int regno)
  222. {
  223.   const struct target_desc *tdesc;

  225.   if (get_usrregs_info ()->regmap[regno] == -1)
  226.     return 1;

  228.   tdesc = current_process ()->tdesc;

  230.   if (find_regno (tdesc, "r0") == regno)
  231.     return 1;

  233.   if (find_regno (tdesc, "cause") == regno)
  234.     return 1;

  236.   if (find_regno (tdesc, "badvaddr") == regno)
  237.     return 1;

  239.   if (find_regno (tdesc, "fir") == regno)
  240.     return 1;

  242.   return 0;
  243. }

  245. static CORE_ADDR
  246. ‌mips_get_pc (struct regcache *regcache)
  247. {
  248.   union mips_register pc;
  249.   collect_register_by_name (regcache, "pc", pc.buf);
  250.   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
  251. }

  253. static void
  254. ‌mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
  255. {
  256.   union mips_register newpc;
  257.   if (register_size (regcache->tdesc, 0) == 4)
  258.     newpc.reg32 = pc;
  259.   else
  260.     newpc.reg64 = pc;

  262.   supply_register_by_name (regcache, "pc", newpc.buf);
  263. }

  265. /* Correct in either endianness.  */
  266. ‌static const unsigned int mips_breakpoint = 0x0005000d;
  267. ‌#define mips_breakpoint_len 4

  269. /* We only place breakpoints in empty marker functions, and thread locking
  270.    is outside of the function.  So rather than importing software single-step,
  271.    we can just run until exit.  */
  272. static CORE_ADDR
  273. ‌mips_reinsert_addr (void)
  274. {
  275.   struct regcache *regcache = get_thread_regcache (current_thread, 1);
  276.   union mips_register ra;
  277.   collect_register_by_name (regcache, "r31", ra.buf);
  278.   return register_size (regcache->tdesc, 0) == 4 ? ra.reg32 : ra.reg64;
  279. }

  281. static int
  282. ‌mips_breakpoint_at (CORE_ADDR where)
  283. {
  284.   unsigned int insn;

  286.   (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
  287.   if (insn == mips_breakpoint)
  288.     return 1;

  290.   /* If necessary, recognize more trap instructions here.  GDB only uses the
  291.      one.  */
  292.   return 0;
  293. }

  295. /* Mark the watch registers of lwp, represented by ENTRY, as changed,
  296.    if the lwp's process id is *PID_P.  */

  298. static int
  299. ‌update_watch_registers_callback (struct inferior_list_entry *entry,
  300.                                  void *pid_p)
  301. {
  302.   struct thread_info *thread = (struct thread_info *) entry;
  303.   struct lwp_info *lwp = get_thread_lwp (thread);
  304.   int pid = *(int *) pid_p;

  306.   /* Only update the threads of this process.  */
  307.   if (pid_of (thread) == pid)
  308.     {
  309.       /* The actual update is done later just before resuming the lwp,
  310.          we just mark that the registers need updating.  */
  311.       lwp->arch_private->watch_registers_changed = 1;

  313.       /* If the lwp isn't stopped, force it to momentarily pause, so
  314.          we can update its watch registers.  */
  315.       if (!lwp->stopped)
  316.         linux_stop_lwp (lwp);
  317.     }

  319.   return 0;
  320. }

  322. /* This is the implementation of linux_target_ops method
  323.    new_process.  */

  325. static struct arch_process_info *
  326. ‌mips_linux_new_process (void)
  327. {
  328.   struct arch_process_info *info = xcalloc (1, sizeof (*info));

  330.   return info;
  331. }

  333. /* This is the implementation of linux_target_ops method new_thread.
  334.    Mark the watch registers as changed, so the threads' copies will
  335.    be updated.  */

  337. static struct arch_lwp_info *
  338. ‌mips_linux_new_thread (void)
  339. {
  340.   struct arch_lwp_info *info = xcalloc (1, sizeof (*info));

  342.   info->watch_registers_changed = 1;

  344.   return info;
  345. }

  347. /* This is the implementation of linux_target_ops method
  348.    prepare_to_resume.  If the watch regs have changed, update the
  349.    thread's copies.  */

  351. static void
  352. ‌mips_linux_prepare_to_resume (struct lwp_info *lwp)
  353. {
  354.   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
  355.   struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
  356.   struct arch_process_info *private = proc->private->arch_private;

  358.   if (lwp->arch_private->watch_registers_changed)
  359.     {
  360.       /* Only update the watch registers if we have set or unset a
  361.          watchpoint already.  */
  362.       if (mips_linux_watch_get_num_valid (&private->watch_mirror) > 0)
  363.         {
  364.           /* Write the mirrored watch register values.  */
  365.           int tid = ptid_get_lwp (ptid);

  367.           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
  368.                             &private->watch_mirror))
  369.             perror_with_name ("Couldn't write watch register");
  370.         }

  372.       lwp->arch_private->watch_registers_changed = 0;
  373.     }
  374. }

  376. static int
  377. ‌mips_supports_z_point_type (char z_type)
  378. {
  379.   switch (z_type)
  380.     {
  381.     case Z_PACKET_WRITE_WP:
  382.     case Z_PACKET_READ_WP:
  383.     case Z_PACKET_ACCESS_WP:
  384.       return 1;
  385.     default:
  386.       return 0;
  387.     }
  388. }

  390. /* This is the implementation of linux_target_ops method
  391.    insert_point.  */

  393. static int
  394. ‌mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
  395.                    int len, struct raw_breakpoint *bp)
  396. {
  397.   struct process_info *proc = current_process ();
  398.   struct arch_process_info *private = proc->private->arch_private;
  399.   struct pt_watch_regs regs;
  400.   struct mips_watchpoint *new_watch;
  401.   struct mips_watchpoint **pw;
  402.   int pid;
  403.   long lwpid;
  404.   enum target_hw_bp_type watch_type;
  405.   uint32_t irw;

  407.   lwpid = lwpid_of (current_thread);
  408.   if (!mips_linux_read_watch_registers (lwpid,
  409.                                         &private->watch_readback,
  410.                                         &private->watch_readback_valid,
  411.                                         0))
  412.     return -1;

  414.   if (len <= 0)
  415.     return -1;

  417.   regs = private->watch_readback;
  418.   /* Add the current watches.  */
  419.   mips_linux_watch_populate_regs (private->current_watches, &regs);

  421.   /* Now try to add the new watch.  */
  422.   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
  423.   irw = mips_linux_watch_type_to_irw (watch_type);
  424.   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
  425.     return -1;

  427.   /* It fit.  Stick it on the end of the list.  */
  428.   new_watch = xmalloc (sizeof (struct mips_watchpoint));
  429.   new_watch->addr = addr;
  430.   new_watch->len = len;
  431.   new_watch->type = watch_type;
  432.   new_watch->next = NULL;

  434.   pw = &private->current_watches;
  435.   while (*pw != NULL)
  436.     pw = &(*pw)->next;
  437.   *pw = new_watch;

  439.   private->watch_mirror = regs;

  441.   /* Only update the threads of this process.  */
  442.   pid = pid_of (proc);
  443.   find_inferior (&all_threads, update_watch_registers_callback, &pid);

  445.   return 0;
  446. }

  448. /* This is the implementation of linux_target_ops method
  449.    remove_point.  */

  451. static int
  452. ‌mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
  453.                    int len, struct raw_breakpoint *bp)
  454. {
  455.   struct process_info *proc = current_process ();
  456.   struct arch_process_info *private = proc->private->arch_private;

  458.   int deleted_one;
  459.   int pid;
  460.   enum target_hw_bp_type watch_type;

  462.   struct mips_watchpoint **pw;
  463.   struct mips_watchpoint *w;

  465.   /* Search for a known watch that matches.  Then unlink and free it.  */
  466.   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
  467.   deleted_one = 0;
  468.   pw = &private->current_watches;
  469.   while ((w = *pw))
  470.     {
  471.       if (w->addr == addr && w->len == len && w->type == watch_type)
  472.         {
  473.           *pw = w->next;
  474.           free (w);
  475.           deleted_one = 1;
  476.           break;
  477.         }
  478.       pw = &(w->next);
  479.     }

  481.   if (!deleted_one)
  482.     return -1;  /* We don't know about it, fail doing nothing.  */

  484.   /* At this point watch_readback is known to be valid because we
  485.      could not have added the watch without reading it.  */
  486.   gdb_assert (private->watch_readback_valid == 1);

  488.   private->watch_mirror = private->watch_readback;
  489.   mips_linux_watch_populate_regs (private->current_watches,
  490.                                   &private->watch_mirror);

  492.   /* Only update the threads of this process.  */
  493.   pid = pid_of (proc);
  494.   find_inferior (&all_threads, update_watch_registers_callback, &pid);
  495.   return 0;
  496. }

  498. /* This is the implementation of linux_target_ops method
  499.    stopped_by_watchpoint.  The watchhi R and W bits indicate
  500.    the watch register triggered. */

  502. static int
  503. ‌mips_stopped_by_watchpoint (void)
  504. {
  505.   struct process_info *proc = current_process ();
  506.   struct arch_process_info *private = proc->private->arch_private;
  507.   int n;
  508.   int num_valid;
  509.   long lwpid = lwpid_of (current_thread);

  511.   if (!mips_linux_read_watch_registers (lwpid,
  512.                                         &private->watch_readback,
  513.                                         &private->watch_readback_valid,
  514.                                         1))
  515.     return 0;

  517.   num_valid = mips_linux_watch_get_num_valid (&private->watch_readback);

  519.   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
  520.     if (mips_linux_watch_get_watchhi (&private->watch_readback, n)
  521.         & (R_MASK | W_MASK))
  522.       return 1;

  524.   return 0;
  525. }

  527. /* This is the implementation of linux_target_ops method
  528.    stopped_data_address.  */

  530. static CORE_ADDR
  531. ‌mips_stopped_data_address (void)
  532. {
  533.   struct process_info *proc = current_process ();
  534.   struct arch_process_info *private = proc->private->arch_private;
  535.   int n;
  536.   int num_valid;
  537.   long lwpid = lwpid_of (current_thread);

  539.   /* On MIPS we don't know the low order 3 bits of the data address.
  540.      GDB does not support remote targets that can't report the
  541.      watchpoint address.  So, make our best guess; return the starting
  542.      address of a watchpoint request which overlaps the one that
  543.      triggered.  */

  545.   if (!mips_linux_read_watch_registers (lwpid,
  546.                                         &private->watch_readback,
  547.                                         &private->watch_readback_valid,
  548.                                         0))
  549.     return 0;

  551.   num_valid = mips_linux_watch_get_num_valid (&private->watch_readback);

  553.   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
  554.     if (mips_linux_watch_get_watchhi (&private->watch_readback, n)
  555.         & (R_MASK | W_MASK))
  556.       {
  557.         CORE_ADDR t_low, t_hi;
  558.         int t_irw;
  559.         struct mips_watchpoint *watch;

  561.         t_low = mips_linux_watch_get_watchlo (&private->watch_readback, n);
  562.         t_irw = t_low & IRW_MASK;
  563.         t_hi = (mips_linux_watch_get_watchhi (&private->watch_readback, n)
  564.                 | IRW_MASK);
  565.         t_low &= ~(CORE_ADDR)t_hi;

  567.         for (watch = private->current_watches;
  568.              watch != NULL;
  569.              watch = watch->next)
  570.           {
  571.             CORE_ADDR addr = watch->addr;
  572.             CORE_ADDR last_byte = addr + watch->len - 1;

  574.             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
  575.               {
  576.                 /* Different type.  */
  577.                 continue;
  578.               }
  579.             /* Check for overlap of even a single byte.  */
  580.             if (last_byte >= t_low && addr <= t_low + t_hi)
  581.               return addr;
  582.           }
  583.       }

  585.   /* Shouldn't happen.  */
  586.   return 0;
  587. }

  589. /* Fetch the thread-local storage pointer for libthread_db.  */

  591. ps_err_e
  592. ‌ps_get_thread_area (const struct ps_prochandle *ph,
  593.                     lwpid_t lwpid, int idx, void **base)
  594. {
  595.   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
  596.     return PS_ERR;

  598.   /* IDX is the bias from the thread pointer to the beginning of the
  599.      thread descriptor.  It has to be subtracted due to implementation
  600.      quirks in libthread_db.  */
  601.   *base = (void *) ((char *)*base - idx);

  603.   return PS_OK;
  604. }

  606. #ifdef HAVE_PTRACE_GETREGS

  608. static void
  609. ‌mips_collect_register (struct regcache *regcache,
  610.                        int use_64bit, int regno, union mips_register *reg)
  611. {
  612.   union mips_register tmp_reg;

  614.   if (use_64bit)
  615.     {
  616.       collect_register (regcache, regno, &tmp_reg.reg64);
  617.       *reg = tmp_reg;
  618.     }
  619.   else
  620.     {
  621.       collect_register (regcache, regno, &tmp_reg.reg32);
  622.       reg->reg64 = tmp_reg.reg32;
  623.     }
  624. }

  626. static void
  627. ‌mips_supply_register (struct regcache *regcache,
  628.                       int use_64bit, int regno, const union mips_register *reg)
  629. {
  630.   int offset = 0;

  632.   /* For big-endian 32-bit targets, ignore the high four bytes of each
  633.      eight-byte slot.  */
  634.   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
  635.     offset = 4;

  637.   supply_register (regcache, regno, reg->buf + offset);
  638. }

  640. static void
  641. ‌mips_collect_register_32bit (struct regcache *regcache,
  642.                              int use_64bit, int regno, unsigned char *buf)
  643. {
  644.   union mips_register tmp_reg;
  645.   int reg32;

  647.   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
  648.   reg32 = tmp_reg.reg64;
  649.   memcpy (buf, &reg32, 4);
  650. }

  652. static void
  653. ‌mips_supply_register_32bit (struct regcache *regcache,
  654.                             int use_64bit, int regno, const unsigned char *buf)
  655. {
  656.   union mips_register tmp_reg;
  657.   int reg32;

  659.   memcpy (&reg32, buf, 4);
  660.   tmp_reg.reg64 = reg32;
  661.   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
  662. }

  664. static void
  665. ‌mips_fill_gregset (struct regcache *regcache, void *buf)
  666. {
  667.   union mips_register *regset = buf;
  668.   int i, use_64bit;
  669.   const struct target_desc *tdesc = regcache->tdesc;

  671.   use_64bit = (register_size (tdesc, 0) == 8);

  673.   for (i = 1; i < 32; i++)
  674.     mips_collect_register (regcache, use_64bit, i, regset + i);

  676.   mips_collect_register (regcache, use_64bit,
  677.                          find_regno (tdesc, "lo"), regset + 32);
  678.   mips_collect_register (regcache, use_64bit,
  679.                          find_regno (tdesc, "hi"), regset + 33);
  680.   mips_collect_register (regcache, use_64bit,
  681.                          find_regno (tdesc, "pc"), regset + 34);
  682.   mips_collect_register (regcache, use_64bit,
  683.                          find_regno (tdesc, "badvaddr"), regset + 35);
  684.   mips_collect_register (regcache, use_64bit,
  685.                          find_regno (tdesc, "status"), regset + 36);
  686.   mips_collect_register (regcache, use_64bit,
  687.                          find_regno (tdesc, "cause"), regset + 37);

  689.   mips_collect_register (regcache, use_64bit,
  690.                          find_regno (tdesc, "restart"), regset + 0);
  691. }

  693. static void
  694. ‌mips_store_gregset (struct regcache *regcache, const void *buf)
  695. {
  696.   const union mips_register *regset = buf;
  697.   int i, use_64bit;

  699.   use_64bit = (register_size (regcache->tdesc, 0) == 8);

  701.   for (i = 0; i < 32; i++)
  702.     mips_supply_register (regcache, use_64bit, i, regset + i);

  704.   mips_supply_register (regcache, use_64bit,
  705.                         find_regno (regcache->tdesc, "lo"), regset + 32);
  706.   mips_supply_register (regcache, use_64bit,
  707.                         find_regno (regcache->tdesc, "hi"), regset + 33);
  708.   mips_supply_register (regcache, use_64bit,
  709.                         find_regno (regcache->tdesc, "pc"), regset + 34);
  710.   mips_supply_register (regcache, use_64bit,
  711.                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
  712.   mips_supply_register (regcache, use_64bit,
  713.                         find_regno (regcache->tdesc, "status"), regset + 36);
  714.   mips_supply_register (regcache, use_64bit,
  715.                         find_regno (regcache->tdesc, "cause"), regset + 37);

  717.   mips_supply_register (regcache, use_64bit,
  718.                         find_regno (regcache->tdesc, "restart"), regset + 0);
  719. }

  721. static void
  722. ‌mips_fill_fpregset (struct regcache *regcache, void *buf)
  723. {
  724.   union mips_register *regset = buf;
  725.   int i, use_64bit, first_fp, big_endian;

  727.   use_64bit = (register_size (regcache->tdesc, 0) == 8);
  728.   first_fp = find_regno (regcache->tdesc, "f0");
  729.   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);

  731.   /* See GDB for a discussion of this peculiar layout.  */
  732.   for (i = 0; i < 32; i++)
  733.     if (use_64bit)
  734.       collect_register (regcache, first_fp + i, regset[i].buf);
  735.     else
  736.       collect_register (regcache, first_fp + i,
  737.                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));

  739.   mips_collect_register_32bit (regcache, use_64bit,
  740.                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
  741.   mips_collect_register_32bit (regcache, use_64bit,
  742.                                find_regno (regcache->tdesc, "fir"),
  743.                                regset[32].buf + 4);
  744. }

  746. static void
  747. ‌mips_store_fpregset (struct regcache *regcache, const void *buf)
  748. {
  749.   const union mips_register *regset = buf;
  750.   int i, use_64bit, first_fp, big_endian;

  752.   use_64bit = (register_size (regcache->tdesc, 0) == 8);
  753.   first_fp = find_regno (regcache->tdesc, "f0");
  754.   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);

  756.   /* See GDB for a discussion of this peculiar layout.  */
  757.   for (i = 0; i < 32; i++)
  758.     if (use_64bit)
  759.       supply_register (regcache, first_fp + i, regset[i].buf);
  760.     else
  761.       supply_register (regcache, first_fp + i,
  762.                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));

  764.   mips_supply_register_32bit (regcache, use_64bit,
  765.                               find_regno (regcache->tdesc, "fcsr"),
  766.                               regset[32].buf);
  767.   mips_supply_register_32bit (regcache, use_64bit,
  768.                               find_regno (regcache->tdesc, "fir"),
  769.                               regset[32].buf + 4);
  770. }
  771. #endif /* HAVE_PTRACE_GETREGS */

  773. ‌static struct regset_info mips_regsets[] = {
  774. #ifdef HAVE_PTRACE_GETREGS
  775.   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
  776.     mips_fill_gregset, mips_store_gregset },
  777.   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
  778.     mips_fill_fpregset, mips_store_fpregset },
  779. #endif /* HAVE_PTRACE_GETREGS */
  780.   { 0, 0, 0, -1, -1, NULL, NULL }
  781. };

  783. ‌static struct regsets_info mips_regsets_info =
  784.   {
  785.     mips_regsets, /* regsets */
  786.     0, /* num_regsets */
  787.     NULL, /* disabled_regsets */
  788.   };

  790. ‌static struct usrregs_info mips_dsp_usrregs_info =
  791.   {
  792.     mips_dsp_num_regs,
  793.     mips_dsp_regmap,
  794.   };

  796. ‌static struct usrregs_info mips_usrregs_info =
  797.   {
  798.     mips_num_regs,
  799.     mips_regmap,
  800.   };

  802. ‌static struct regs_info dsp_regs_info =
  803.   {
  804.     mips_dsp_regset_bitmap,
  805.     &mips_dsp_usrregs_info,
  806.     &mips_regsets_info
  807.   };

  809. ‌static struct regs_info regs_info =
  810.   {
  811.     NULL, /* regset_bitmap */
  812.     &mips_usrregs_info,
  813.     &mips_regsets_info
  814.   };

  816. static const struct regs_info *
  817. ‌mips_regs_info (void)
  818. {
  819.   if (have_dsp)
  820.     return &dsp_regs_info;
  821.   else
  822.     return &regs_info;
  823. }

  825. ‌struct linux_target_ops the_low_target = {
  826.   mips_arch_setup,
  827.   mips_regs_info,
  828.   mips_cannot_fetch_register,
  829.   mips_cannot_store_register,
  830.   NULL, /* fetch_register */
  831.   mips_get_pc,
  832.   mips_set_pc,
  833.   (const unsigned char *) &mips_breakpoint,
  834.   mips_breakpoint_len,
  835.   mips_reinsert_addr,
  836.   0,
  837.   mips_breakpoint_at,
  838.   mips_supports_z_point_type,
  839.   mips_insert_point,
  840.   mips_remove_point,
  841.   mips_stopped_by_watchpoint,
  842.   mips_stopped_data_address,
  843.   NULL,
  844.   NULL,
  845.   NULL, /* siginfo_fixup */
  846.   mips_linux_new_process,
  847.   mips_linux_new_thread,
  848.   mips_linux_prepare_to_resume
  849. };

  851. void
  852. ‌initialize_low_arch (void)
  853. {
  854.   /* Initialize the Linux target descriptions.  */
  855.   init_registers_mips_linux ();
  856.   init_registers_mips_dsp_linux ();
  857.   init_registers_mips64_linux ();
  858.   init_registers_mips64_dsp_linux ();

  860.   initialize_regsets_info (&mips_regsets_info);
  861. }