gdb/amd64-tdep.c - gdb

Global variables defined

Data types defined

Functions defined

Macros defined

Source code

  1. /* Target-dependent code for AMD64.

  3.    Copyright (C) 2001-2015 Free Software Foundation, Inc.

  5.    Contributed by Jiri Smid, SuSE Labs.

  7.    This file is part of GDB.

  9.    This program is free software; you can redistribute it and/or modify
  10.    it under the terms of the GNU General Public License as published by
  11.    the Free Software Foundation; either version 3 of the License, or
  12.    (at your option) any later version.

  14.    This program is distributed in the hope that it will be useful,
  15.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17.    GNU General Public License for more details.

  19.    You should have received a copy of the GNU General Public License
  20.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  22. #include "defs.h"
  23. #include "opcode/i386.h"
  24. #include "dis-asm.h"
  25. #include "arch-utils.h"
  26. #include "block.h"
  27. #include "dummy-frame.h"
  28. #include "frame.h"
  29. #include "frame-base.h"
  30. #include "frame-unwind.h"
  31. #include "inferior.h"
  32. #include "infrun.h"
  33. #include "gdbcmd.h"
  34. #include "gdbcore.h"
  35. #include "objfiles.h"
  36. #include "regcache.h"
  37. #include "regset.h"
  38. #include "symfile.h"
  39. #include "disasm.h"
  40. #include "amd64-tdep.h"
  41. #include "i387-tdep.h"

  43. #include "features/i386/amd64.c"
  44. #include "features/i386/amd64-avx.c"
  45. #include "features/i386/amd64-mpx.c"
  46. #include "features/i386/amd64-avx512.c"

  48. #include "features/i386/x32.c"
  49. #include "features/i386/x32-avx.c"
  50. #include "features/i386/x32-avx512.c"

  52. #include "ax.h"
  53. #include "ax-gdb.h"

  55. /* Note that the AMD64 architecture was previously known as x86-64.
  56.    The latter is (forever) engraved into the canonical system name as
  57.    returned by config.guess, and used as the name for the AMD64 port
  58.    of GNU/Linux.  The BSD's have renamed their ports to amd64; they
  59.    don't like to shout.  For GDB we prefer the amd64_-prefix over the
  60.    x86_64_-prefix since it's so much easier to type.  */

  62. /* Register information.  */

  64. ‌static const char *amd64_register_names[] =
  65. {
  66.   "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",

  68.   /* %r8 is indeed register number 8.  */
  69.   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  70.   "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",

  72.   /* %st0 is register number 24.  */
  73.   "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
  74.   "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",

  76.   /* %xmm0 is register number 40.  */
  77.   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
  78.   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
  79.   "mxcsr",
  80. };

  82. ‌static const char *amd64_ymm_names[] =
  83. {
  84.   "ymm0", "ymm1", "ymm2", "ymm3",
  85.   "ymm4", "ymm5", "ymm6", "ymm7",
  86.   "ymm8", "ymm9", "ymm10", "ymm11",
  87.   "ymm12", "ymm13", "ymm14", "ymm15"
  88. };

  90. ‌static const char *amd64_ymm_avx512_names[] =
  91. {
  92.   "ymm16", "ymm17", "ymm18", "ymm19",
  93.   "ymm20", "ymm21", "ymm22", "ymm23",
  94.   "ymm24", "ymm25", "ymm26", "ymm27",
  95.   "ymm28", "ymm29", "ymm30", "ymm31"
  96. };

  98. ‌static const char *amd64_ymmh_names[] =
  99. {
  100.   "ymm0h", "ymm1h", "ymm2h", "ymm3h",
  101.   "ymm4h", "ymm5h", "ymm6h", "ymm7h",
  102.   "ymm8h", "ymm9h", "ymm10h", "ymm11h",
  103.   "ymm12h", "ymm13h", "ymm14h", "ymm15h"
  104. };

  106. ‌static const char *amd64_ymmh_avx512_names[] =
  107. {
  108.   "ymm16h", "ymm17h", "ymm18h", "ymm19h",
  109.   "ymm20h", "ymm21h", "ymm22h", "ymm23h",
  110.   "ymm24h", "ymm25h", "ymm26h", "ymm27h",
  111.   "ymm28h", "ymm29h", "ymm30h", "ymm31h"
  112. };

  114. ‌static const char *amd64_mpx_names[] =
  115. {
  116.   "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
  117. };

  119. ‌static const char *amd64_k_names[] =
  120. {
  121.   "k0", "k1", "k2", "k3",
  122.   "k4", "k5", "k6", "k7"
  123. };

  125. ‌static const char *amd64_zmmh_names[] =
  126. {
  127.   "zmm0h", "zmm1h", "zmm2h", "zmm3h",
  128.   "zmm4h", "zmm5h", "zmm6h", "zmm7h",
  129.   "zmm8h", "zmm9h", "zmm10h", "zmm11h",
  130.   "zmm12h", "zmm13h", "zmm14h", "zmm15h",
  131.   "zmm16h", "zmm17h", "zmm18h", "zmm19h",
  132.   "zmm20h", "zmm21h", "zmm22h", "zmm23h",
  133.   "zmm24h", "zmm25h", "zmm26h", "zmm27h",
  134.   "zmm28h", "zmm29h", "zmm30h", "zmm31h"
  135. };

  137. ‌static const char *amd64_zmm_names[] =
  138. {
  139.   "zmm0", "zmm1", "zmm2", "zmm3",
  140.   "zmm4", "zmm5", "zmm6", "zmm7",
  141.   "zmm8", "zmm9", "zmm10", "zmm11",
  142.   "zmm12", "zmm13", "zmm14", "zmm15",
  143.   "zmm16", "zmm17", "zmm18", "zmm19",
  144.   "zmm20", "zmm21", "zmm22", "zmm23",
  145.   "zmm24", "zmm25", "zmm26", "zmm27",
  146.   "zmm28", "zmm29", "zmm30", "zmm31"
  147. };

  149. ‌static const char *amd64_xmm_avx512_names[] = {
  150.     "xmm16",  "xmm17",  "xmm18",  "xmm19",
  151.     "xmm20",  "xmm21",  "xmm22",  "xmm23",
  152.     "xmm24",  "xmm25",  "xmm26",  "xmm27",
  153.     "xmm28",  "xmm29",  "xmm30",  "xmm31"
  154. };

  156. /* DWARF Register Number Mapping as defined in the System V psABI,
  157.    section 3.6.  */

  159. ‌static int amd64_dwarf_regmap[] =
  160. {
  161.   /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI.  */
  162.   AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
  163.   AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
  164.   AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,

  166.   /* Frame Pointer Register RBP.  */
  167.   AMD64_RBP_REGNUM,

  169.   /* Stack Pointer Register RSP.  */
  170.   AMD64_RSP_REGNUM,

  172.   /* Extended Integer Registers 8 - 15.  */
  173.   AMD64_R8_REGNUM,                /* %r8 */
  174.   AMD64_R9_REGNUM,                /* %r9 */
  175.   AMD64_R10_REGNUM,                /* %r10 */
  176.   AMD64_R11_REGNUM,                /* %r11 */
  177.   AMD64_R12_REGNUM,                /* %r12 */
  178.   AMD64_R13_REGNUM,                /* %r13 */
  179.   AMD64_R14_REGNUM,                /* %r14 */
  180.   AMD64_R15_REGNUM,                /* %r15 */

  182.   /* Return Address RA.  Mapped to RIP.  */
  183.   AMD64_RIP_REGNUM,

  185.   /* SSE Registers 0 - 7.  */
  186.   AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
  187.   AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
  188.   AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
  189.   AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,

  191.   /* Extended SSE Registers 8 - 15.  */
  192.   AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
  193.   AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
  194.   AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
  195.   AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,

  197.   /* Floating Point Registers 0-7.  */
  198.   AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
  199.   AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
  200.   AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
  201.   AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,

  203.   /* MMX Registers 0 - 7.
  204.      We have to handle those registers specifically, as their register
  205.      number within GDB depends on the target (or they may even not be
  206.      available at all).  */
  207.   -1, -1, -1, -1, -1, -1, -1, -1,

  209.   /* Control and Status Flags Register.  */
  210.   AMD64_EFLAGS_REGNUM,

  212.   /* Selector Registers.  */
  213.   AMD64_ES_REGNUM,
  214.   AMD64_CS_REGNUM,
  215.   AMD64_SS_REGNUM,
  216.   AMD64_DS_REGNUM,
  217.   AMD64_FS_REGNUM,
  218.   AMD64_GS_REGNUM,
  219.   -1,
  220.   -1,

  222.   /* Segment Base Address Registers.  */
  223.   -1,
  224.   -1,
  225.   -1,
  226.   -1,

  228.   /* Special Selector Registers.  */
  229.   -1,
  230.   -1,

  232.   /* Floating Point Control Registers.  */
  233.   AMD64_MXCSR_REGNUM,
  234.   AMD64_FCTRL_REGNUM,
  235.   AMD64_FSTAT_REGNUM
  236. };

  238. ‌static const int amd64_dwarf_regmap_len =
  239.   (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));

  241. /* Convert DWARF register number REG to the appropriate register
  242.    number used by GDB.  */

  244. static int
  245. ‌amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
  246. {
  247.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  248.   int ymm0_regnum = tdep->ymm0_regnum;
  249.   int regnum = -1;

  251.   if (reg >= 0 && reg < amd64_dwarf_regmap_len)
  252.     regnum = amd64_dwarf_regmap[reg];

  254.   if (regnum == -1)
  255.     warning (_("Unmapped DWARF Register #%d encountered."), reg);
  256.   else if (ymm0_regnum >= 0
  257.            && i386_xmm_regnum_p (gdbarch, regnum))
  258.     regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);

  260.   return regnum;
  261. }

  263. /* Map architectural register numbers to gdb register numbers.  */

  265. ‌static const int amd64_arch_regmap[16] =
  266. {
  267.   AMD64_RAX_REGNUM,        /* %rax */
  268.   AMD64_RCX_REGNUM,        /* %rcx */
  269.   AMD64_RDX_REGNUM,        /* %rdx */
  270.   AMD64_RBX_REGNUM,        /* %rbx */
  271.   AMD64_RSP_REGNUM,        /* %rsp */
  272.   AMD64_RBP_REGNUM,        /* %rbp */
  273.   AMD64_RSI_REGNUM,        /* %rsi */
  274.   AMD64_RDI_REGNUM,        /* %rdi */
  275.   AMD64_R8_REGNUM,        /* %r8 */
  276.   AMD64_R9_REGNUM,        /* %r9 */
  277.   AMD64_R10_REGNUM,        /* %r10 */
  278.   AMD64_R11_REGNUM,        /* %r11 */
  279.   AMD64_R12_REGNUM,        /* %r12 */
  280.   AMD64_R13_REGNUM,        /* %r13 */
  281.   AMD64_R14_REGNUM,        /* %r14 */
  282.   AMD64_R15_REGNUM        /* %r15 */
  283. };

  285. ‌static const int amd64_arch_regmap_len =
  286.   (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));

  288. /* Convert architectural register number REG to the appropriate register
  289.    number used by GDB.  */

  291. static int
  292. ‌amd64_arch_reg_to_regnum (int reg)
  293. {
  294.   gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);

  296.   return amd64_arch_regmap[reg];
  297. }

  299. /* Register names for byte pseudo-registers.  */

  301. ‌static const char *amd64_byte_names[] =
  302. {
  303.   "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
  304.   "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
  305.   "ah", "bh", "ch", "dh"
  306. };

  308. /* Number of lower byte registers.  */
  309. ‌#define AMD64_NUM_LOWER_BYTE_REGS 16

  311. /* Register names for word pseudo-registers.  */

  313. ‌static const char *amd64_word_names[] =
  314. {
  315.   "ax", "bx", "cx", "dx", "si", "di", "bp", "",
  316.   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
  317. };

  319. /* Register names for dword pseudo-registers.  */

  321. ‌static const char *amd64_dword_names[] =
  322. {
  323.   "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
  324.   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
  325.   "eip"
  326. };

  328. /* Return the name of register REGNUM.  */

  330. static const char *
  331. ‌amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
  332. {
  333.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  334.   if (i386_byte_regnum_p (gdbarch, regnum))
  335.     return amd64_byte_names[regnum - tdep->al_regnum];
  336.   else if (i386_zmm_regnum_p (gdbarch, regnum))
  337.     return amd64_zmm_names[regnum - tdep->zmm0_regnum];
  338.   else if (i386_ymm_regnum_p (gdbarch, regnum))
  339.     return amd64_ymm_names[regnum - tdep->ymm0_regnum];
  340.   else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
  341.     return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
  342.   else if (i386_word_regnum_p (gdbarch, regnum))
  343.     return amd64_word_names[regnum - tdep->ax_regnum];
  344.   else if (i386_dword_regnum_p (gdbarch, regnum))
  345.     return amd64_dword_names[regnum - tdep->eax_regnum];
  346.   else
  347.     return i386_pseudo_register_name (gdbarch, regnum);
  348. }

  350. static struct value *
  351. ‌amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
  352.                                   struct regcache *regcache,
  353.                                   int regnum)
  354. {
  355.   gdb_byte raw_buf[MAX_REGISTER_SIZE];
  356.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  357.   enum register_status status;
  358.   struct value *result_value;
  359.   gdb_byte *buf;

  361.   result_value = allocate_value (register_type (gdbarch, regnum));
  362.   VALUE_LVAL (result_value) = lval_register;
  363.   VALUE_REGNUM (result_value) = regnum;
  364.   buf = value_contents_raw (result_value);

  366.   if (i386_byte_regnum_p (gdbarch, regnum))
  367.     {
  368.       int gpnum = regnum - tdep->al_regnum;

  370.       /* Extract (always little endian).  */
  371.       if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
  372.         {
  373.           /* Special handling for AH, BH, CH, DH.  */
  374.           status = regcache_raw_read (regcache,
  375.                                       gpnum - AMD64_NUM_LOWER_BYTE_REGS,
  376.                                       raw_buf);
  377.           if (status == REG_VALID)
  378.             memcpy (buf, raw_buf + 1, 1);
  379.           else
  380.             mark_value_bytes_unavailable (result_value, 0,
  381.                                           TYPE_LENGTH (value_type (result_value)));
  382.         }
  383.       else
  384.         {
  385.           status = regcache_raw_read (regcache, gpnum, raw_buf);
  386.           if (status == REG_VALID)
  387.             memcpy (buf, raw_buf, 1);
  388.           else
  389.             mark_value_bytes_unavailable (result_value, 0,
  390.                                           TYPE_LENGTH (value_type (result_value)));
  391.         }
  392.     }
  393.   else if (i386_dword_regnum_p (gdbarch, regnum))
  394.     {
  395.       int gpnum = regnum - tdep->eax_regnum;
  396.       /* Extract (always little endian).  */
  397.       status = regcache_raw_read (regcache, gpnum, raw_buf);
  398.       if (status == REG_VALID)
  399.         memcpy (buf, raw_buf, 4);
  400.       else
  401.         mark_value_bytes_unavailable (result_value, 0,
  402.                                       TYPE_LENGTH (value_type (result_value)));
  403.     }
  404.   else
  405.     i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
  406.                                           result_value);

  408.   return result_value;
  409. }

  411. static void
  412. ‌amd64_pseudo_register_write (struct gdbarch *gdbarch,
  413.                              struct regcache *regcache,
  414.                              int regnum, const gdb_byte *buf)
  415. {
  416.   gdb_byte raw_buf[MAX_REGISTER_SIZE];
  417.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  419.   if (i386_byte_regnum_p (gdbarch, regnum))
  420.     {
  421.       int gpnum = regnum - tdep->al_regnum;

  423.       if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
  424.         {
  425.           /* Read ... AH, BH, CH, DH.  */
  426.           regcache_raw_read (regcache,
  427.                              gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
  428.           /* ... Modify ... (always little endian).  */
  429.           memcpy (raw_buf + 1, buf, 1);
  430.           /* ... Write.  */
  431.           regcache_raw_write (regcache,
  432.                               gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
  433.         }
  434.       else
  435.         {
  436.           /* Read ...  */
  437.           regcache_raw_read (regcache, gpnum, raw_buf);
  438.           /* ... Modify ... (always little endian).  */
  439.           memcpy (raw_buf, buf, 1);
  440.           /* ... Write.  */
  441.           regcache_raw_write (regcache, gpnum, raw_buf);
  442.         }
  443.     }
  444.   else if (i386_dword_regnum_p (gdbarch, regnum))
  445.     {
  446.       int gpnum = regnum - tdep->eax_regnum;

  448.       /* Read ...  */
  449.       regcache_raw_read (regcache, gpnum, raw_buf);
  450.       /* ... Modify ... (always little endian).  */
  451.       memcpy (raw_buf, buf, 4);
  452.       /* ... Write.  */
  453.       regcache_raw_write (regcache, gpnum, raw_buf);
  454.     }
  455.   else
  456.     i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
  457. }



  461. /* Register classes as defined in the psABI.  */

  463. ‌enum amd64_reg_class
  464. {
  465.   AMD64_INTEGER,
  466.   AMD64_SSE,
  467.   AMD64_SSEUP,
  468.   AMD64_X87,
  469.   AMD64_X87UP,
  470.   AMD64_COMPLEX_X87,
  471.   AMD64_NO_CLASS,
  472.   AMD64_MEMORY
  473. };

  475. /* Return the union class of CLASS1 and CLASS2.  See the psABI for
  476.    details.  */

  478. static enum amd64_reg_class
  479. ‌amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
  480. {
  481.   /* Rule (a): If both classes are equal, this is the resulting class.  */
  482.   if (class1 == class2)
  483.     return class1;

  485.   /* Rule (b): If one of the classes is NO_CLASS, the resulting class
  486.      is the other class.  */
  487.   if (class1 == AMD64_NO_CLASS)
  488.     return class2;
  489.   if (class2 == AMD64_NO_CLASS)
  490.     return class1;

  492.   /* Rule (c): If one of the classes is MEMORY, the result is MEMORY.  */
  493.   if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
  494.     return AMD64_MEMORY;

  496.   /* Rule (d): If one of the classes is INTEGER, the result is INTEGER.  */
  497.   if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
  498.     return AMD64_INTEGER;

  500.   /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
  501.      MEMORY is used as class.  */
  502.   if (class1 == AMD64_X87 || class1 == AMD64_X87UP
  503.       || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
  504.       || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
  505.     return AMD64_MEMORY;

  507.   /* Rule (f): Otherwise class SSE is used.  */
  508.   return AMD64_SSE;
  509. }

  511. static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);

  513. /* Return non-zero if TYPE is a non-POD structure or union type.  */

  515. static int
  516. ‌amd64_non_pod_p (struct type *type)
  517. {
  518.   /* ??? A class with a base class certainly isn't POD, but does this
  519.      catch all non-POD structure types?  */
  520.   if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
  521.     return 1;

  523.   return 0;
  524. }

  526. /* Classify TYPE according to the rules for aggregate (structures and
  527.    arrays) and union types, and store the result in CLASS.  */

  529. static void
  530. ‌amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
  531. {
  532.   /* 1. If the size of an object is larger than two eightbytes, or in
  533.         C++, is a non-POD structure or union type, or contains
  534.         unaligned fields, it has class memory.  */
  535.   if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
  536.     {
  537.       class[0] = class[1] = AMD64_MEMORY;
  538.       return;
  539.     }

  541.   /* 2. Both eightbytes get initialized to class NO_CLASS.  */
  542.   class[0] = class[1] = AMD64_NO_CLASS;

  544.   /* 3. Each field of an object is classified recursively so that
  545.         always two fields are considered. The resulting class is
  546.         calculated according to the classes of the fields in the
  547.         eightbyte: */

  549.   if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
  550.     {
  551.       struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));

  553.       /* All fields in an array have the same type.  */
  554.       amd64_classify (subtype, class);
  555.       if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS)
  556.         class[1] = class[0];
  557.     }
  558.   else
  559.     {
  560.       int i;

  562.       /* Structure or union.  */
  563.       gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
  564.                   || TYPE_CODE (type) == TYPE_CODE_UNION);

  566.       for (i = 0; i < TYPE_NFIELDS (type); i++)
  567.         {
  568.           struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
  569.           int pos = TYPE_FIELD_BITPOS (type, i) / 64;
  570.           enum amd64_reg_class subclass[2];
  571.           int bitsize = TYPE_FIELD_BITSIZE (type, i);
  572.           int endpos;

  574.           if (bitsize == 0)
  575.             bitsize = TYPE_LENGTH (subtype) * 8;
  576.           endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;

  578.           /* Ignore static fields.  */
  579.           if (field_is_static (&TYPE_FIELD (type, i)))
  580.             continue;

  582.           gdb_assert (pos == 0 || pos == 1);

  584.           amd64_classify (subtype, subclass);
  585.           class[pos] = amd64_merge_classes (class[pos], subclass[0]);
  586.           if (bitsize <= 64 && pos == 0 && endpos == 1)
  587.             /* This is a bit of an odd case:  We have a field that would
  588.                normally fit in one of the two eightbytes, except that
  589.                it is placed in a way that this field straddles them.
  590.                This has been seen with a structure containing an array.

  592.                The ABI is a bit unclear in this case, but we assume that
  593.                this field's class (stored in subclass[0]) must also be merged
  594.                into class[1].  In other words, our field has a piece stored
  595.                in the second eight-byte, and thus its class applies to
  596.                the second eight-byte as well.

  598.                In the case where the field length exceeds 8 bytes,
  599.                it should not be necessary to merge the field class
  600.                into class[1].  As LEN > 8, subclass[1] is necessarily
  601.                different from AMD64_NO_CLASS.  If subclass[1] is equal
  602.                to subclass[0], then the normal class[1]/subclass[1]
  603.                merging will take care of everything.  For subclass[1]
  604.                to be different from subclass[0], I can only see the case
  605.                where we have a SSE/SSEUP or X87/X87UP pair, which both
  606.                use up all 16 bytes of the aggregate, and are already
  607.                handled just fine (because each portion sits on its own
  608.                8-byte).  */
  609.             class[1] = amd64_merge_classes (class[1], subclass[0]);
  610.           if (pos == 0)
  611.             class[1] = amd64_merge_classes (class[1], subclass[1]);
  612.         }
  613.     }

  615.   /* 4. Then a post merger cleanup is done:  */

  617.   /* Rule (a): If one of the classes is MEMORY, the whole argument is
  618.      passed in memory.  */
  619.   if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
  620.     class[0] = class[1] = AMD64_MEMORY;

  622.   /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
  623.      SSE.  */
  624.   if (class[0] == AMD64_SSEUP)
  625.     class[0] = AMD64_SSE;
  626.   if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
  627.     class[1] = AMD64_SSE;
  628. }

  630. /* Classify TYPE, and store the result in CLASS.  */

  632. static void
  633. ‌amd64_classify (struct type *type, enum amd64_reg_class class[2])
  634. {
  635.   enum type_code code = TYPE_CODE (type);
  636.   int len = TYPE_LENGTH (type);

  638.   class[0] = class[1] = AMD64_NO_CLASS;

  640.   /* Arguments of types (signed and unsigned) _Bool, char, short, int,
  641.      long, long long, and pointers are in the INTEGER class.  Similarly,
  642.      range types, used by languages such as Ada, are also in the INTEGER
  643.      class.  */
  644.   if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
  645.        || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
  646.        || code == TYPE_CODE_CHAR
  647.        || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
  648.       && (len == 1 || len == 2 || len == 4 || len == 8))
  649.     class[0] = AMD64_INTEGER;

  651.   /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
  652.      are in class SSE.  */
  653.   else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
  654.            && (len == 4 || len == 8))
  655.     /* FIXME: __m64 .  */
  656.     class[0] = AMD64_SSE;

  658.   /* Arguments of types __float128, _Decimal128 and __m128 are split into
  659.      two halves.  The least significant ones belong to class SSE, the most
  660.      significant one to class SSEUP.  */
  661.   else if (code == TYPE_CODE_DECFLOAT && len == 16)
  662.     /* FIXME: __float128, __m128.  */
  663.     class[0] = AMD64_SSE, class[1] = AMD64_SSEUP;

  665.   /* The 64-bit mantissa of arguments of type long double belongs to
  666.      class X87, the 16-bit exponent plus 6 bytes of padding belongs to
  667.      class X87UP.  */
  668.   else if (code == TYPE_CODE_FLT && len == 16)
  669.     /* Class X87 and X87UP.  */
  670.     class[0] = AMD64_X87, class[1] = AMD64_X87UP;

  672.   /* Arguments of complex T where T is one of the types float or
  673.      double get treated as if they are implemented as:

  675.      struct complexT {
  676.        T real;
  677.        T imag;
  678.      };

  680.   */
  681.   else if (code == TYPE_CODE_COMPLEX && len == 8)
  682.     class[0] = AMD64_SSE;
  683.   else if (code == TYPE_CODE_COMPLEX && len == 16)
  684.     class[0] = class[1] = AMD64_SSE;

  686.   /* A variable of type complex long double is classified as type
  687.      COMPLEX_X87.  */
  688.   else if (code == TYPE_CODE_COMPLEX && len == 32)
  689.     class[0] = AMD64_COMPLEX_X87;

  691.   /* Aggregates.  */
  692.   else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
  693.            || code == TYPE_CODE_UNION)
  694.     amd64_classify_aggregate (type, class);
  695. }

  697. static enum return_value_convention
  698. ‌amd64_return_value (struct gdbarch *gdbarch, struct value *function,
  699.                     struct type *type, struct regcache *regcache,
  700.                     gdb_byte *readbuf, const gdb_byte *writebuf)
  701. {
  702.   enum amd64_reg_class class[2];
  703.   int len = TYPE_LENGTH (type);
  704.   static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
  705.   static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
  706.   int integer_reg = 0;
  707.   int sse_reg = 0;
  708.   int i;

  710.   gdb_assert (!(readbuf && writebuf));

  712.   /* 1. Classify the return type with the classification algorithm.  */
  713.   amd64_classify (type, class);

  715.   /* 2. If the type has class MEMORY, then the caller provides space
  716.      for the return value and passes the address of this storage in
  717.      %rdi as if it were the first argument to the function.  In effect,
  718.      this address becomes a hidden first argument.

  720.      On return %rax will contain the address that has been passed in
  721.      by the caller in %rdi.  */
  722.   if (class[0] == AMD64_MEMORY)
  723.     {
  724.       /* As indicated by the comment above, the ABI guarantees that we
  725.          can always find the return value just after the function has
  726.          returned.  */

  728.       if (readbuf)
  729.         {
  730.           ULONGEST addr;

  732.           regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
  733.           read_memory (addr, readbuf, TYPE_LENGTH (type));
  734.         }

  736.       return RETURN_VALUE_ABI_RETURNS_ADDRESS;
  737.     }

  739.   /* 8. If the class is COMPLEX_X87, the real part of the value is
  740.         returned in %st0 and the imaginary part in %st1.  */
  741.   if (class[0] == AMD64_COMPLEX_X87)
  742.     {
  743.       if (readbuf)
  744.         {
  745.           regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
  746.           regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
  747.         }

  749.       if (writebuf)
  750.         {
  751.           i387_return_value (gdbarch, regcache);
  752.           regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
  753.           regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);

  755.           /* Fix up the tag word such that both %st(0) and %st(1) are
  756.              marked as valid.  */
  757.           regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
  758.         }

  760.       return RETURN_VALUE_REGISTER_CONVENTION;
  761.     }

  763.   gdb_assert (class[1] != AMD64_MEMORY);
  764.   gdb_assert (len <= 16);

  766.   for (i = 0; len > 0; i++, len -= 8)
  767.     {
  768.       int regnum = -1;
  769.       int offset = 0;

  771.       switch (class[i])
  772.         {
  773.         case AMD64_INTEGER:
  774.           /* 3. If the class is INTEGER, the next available register
  775.              of the sequence %rax, %rdx is used.  */
  776.           regnum = integer_regnum[integer_reg++];
  777.           break;

  779.         case AMD64_SSE:
  780.           /* 4. If the class is SSE, the next available SSE register
  781.              of the sequence %xmm0, %xmm1 is used.  */
  782.           regnum = sse_regnum[sse_reg++];
  783.           break;

  785.         case AMD64_SSEUP:
  786.           /* 5. If the class is SSEUP, the eightbyte is passed in the
  787.              upper half of the last used SSE register.  */
  788.           gdb_assert (sse_reg > 0);
  789.           regnum = sse_regnum[sse_reg - 1];
  790.           offset = 8;
  791.           break;

  793.         case AMD64_X87:
  794.           /* 6. If the class is X87, the value is returned on the X87
  795.              stack in %st0 as 80-bit x87 number.  */
  796.           regnum = AMD64_ST0_REGNUM;
  797.           if (writebuf)
  798.             i387_return_value (gdbarch, regcache);
  799.           break;

  801.         case AMD64_X87UP:
  802.           /* 7. If the class is X87UP, the value is returned together
  803.              with the previous X87 value in %st0.  */
  804.           gdb_assert (i > 0 && class[0] == AMD64_X87);
  805.           regnum = AMD64_ST0_REGNUM;
  806.           offset = 8;
  807.           len = 2;
  808.           break;

  810.         case AMD64_NO_CLASS:
  811.           continue;

  813.         default:
  814.           gdb_assert (!"Unexpected register class.");
  815.         }

  817.       gdb_assert (regnum != -1);

  819.       if (readbuf)
  820.         regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
  821.                                 readbuf + i * 8);
  822.       if (writebuf)
  823.         regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
  824.                                  writebuf + i * 8);
  825.     }

  827.   return RETURN_VALUE_REGISTER_CONVENTION;
  828. }


  831. static CORE_ADDR
  832. ‌amd64_push_arguments (struct regcache *regcache, int nargs,
  833.                       struct value **args, CORE_ADDR sp, int struct_return)
  834. {
  835.   static int integer_regnum[] =
  836.   {
  837.     AMD64_RDI_REGNUM,                /* %rdi */
  838.     AMD64_RSI_REGNUM,                /* %rsi */
  839.     AMD64_RDX_REGNUM,                /* %rdx */
  840.     AMD64_RCX_REGNUM,                /* %rcx */
  841.     AMD64_R8_REGNUM,                /* %r8 */
  842.     AMD64_R9_REGNUM                /* %r9 */
  843.   };
  844.   static int sse_regnum[] =
  845.   {
  846.     /* %xmm0 ... %xmm7 */
  847.     AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
  848.     AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
  849.     AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
  850.     AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
  851.   };
  852.   struct value **stack_args = alloca (nargs * sizeof (struct value *));
  853.   int num_stack_args = 0;
  854.   int num_elements = 0;
  855.   int element = 0;
  856.   int integer_reg = 0;
  857.   int sse_reg = 0;
  858.   int i;

  860.   /* Reserve a register for the "hidden" argument.  */
  861.   if (struct_return)
  862.     integer_reg++;

  864.   for (i = 0; i < nargs; i++)
  865.     {
  866.       struct type *type = value_type (args[i]);
  867.       int len = TYPE_LENGTH (type);
  868.       enum amd64_reg_class class[2];
  869.       int needed_integer_regs = 0;
  870.       int needed_sse_regs = 0;
  871.       int j;

  873.       /* Classify argument.  */
  874.       amd64_classify (type, class);

  876.       /* Calculate the number of integer and SSE registers needed for
  877.          this argument.  */
  878.       for (j = 0; j < 2; j++)
  879.         {
  880.           if (class[j] == AMD64_INTEGER)
  881.             needed_integer_regs++;
  882.           else if (class[j] == AMD64_SSE)
  883.             needed_sse_regs++;
  884.         }

  886.       /* Check whether enough registers are available, and if the
  887.          argument should be passed in registers at all.  */
  888.       if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
  889.           || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
  890.           || (needed_integer_regs == 0 && needed_sse_regs == 0))
  891.         {
  892.           /* The argument will be passed on the stack.  */
  893.           num_elements += ((len + 7) / 8);
  894.           stack_args[num_stack_args++] = args[i];
  895.         }
  896.       else
  897.         {
  898.           /* The argument will be passed in registers.  */
  899.           const gdb_byte *valbuf = value_contents (args[i]);
  900.           gdb_byte buf[8];

  902.           gdb_assert (len <= 16);

  904.           for (j = 0; len > 0; j++, len -= 8)
  905.             {
  906.               int regnum = -1;
  907.               int offset = 0;

  909.               switch (class[j])
  910.                 {
  911.                 case AMD64_INTEGER:
  912.                   regnum = integer_regnum[integer_reg++];
  913.                   break;

  915.                 case AMD64_SSE:
  916.                   regnum = sse_regnum[sse_reg++];
  917.                   break;

  919.                 case AMD64_SSEUP:
  920.                   gdb_assert (sse_reg > 0);
  921.                   regnum = sse_regnum[sse_reg - 1];
  922.                   offset = 8;
  923.                   break;

  925.                 default:
  926.                   gdb_assert (!"Unexpected register class.");
  927.                 }

  929.               gdb_assert (regnum != -1);
  930.               memset (buf, 0, sizeof buf);
  931.               memcpy (buf, valbuf + j * 8, min (len, 8));
  932.               regcache_raw_write_part (regcache, regnum, offset, 8, buf);
  933.             }
  934.         }
  935.     }

  937.   /* Allocate space for the arguments on the stack.  */
  938.   sp -= num_elements * 8;

  940.   /* The psABI says that "The end of the input argument area shall be
  941.      aligned on a 16 byte boundary."  */
  942.   sp &= ~0xf;

  944.   /* Write out the arguments to the stack.  */
  945.   for (i = 0; i < num_stack_args; i++)
  946.     {
  947.       struct type *type = value_type (stack_args[i]);
  948.       const gdb_byte *valbuf = value_contents (stack_args[i]);
  949.       int len = TYPE_LENGTH (type);

  951.       write_memory (sp + element * 8, valbuf, len);
  952.       element += ((len + 7) / 8);
  953.     }

  955.   /* The psABI says that "For calls that may call functions that use
  956.      varargs or stdargs (prototype-less calls or calls to functions
  957.      containing ellipsis (...) in the declaration) %al is used as
  958.      hidden argument to specify the number of SSE registers used.  */
  959.   regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
  960.   return sp;
  961. }

  963. static CORE_ADDR
  964. ‌amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
  965.                        struct regcache *regcache, CORE_ADDR bp_addr,
  966.                        int nargs, struct value **args,        CORE_ADDR sp,
  967.                        int struct_return, CORE_ADDR struct_addr)
  968. {
  969.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  970.   gdb_byte buf[8];

  972.   /* Pass arguments.  */
  973.   sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);

  975.   /* Pass "hidden" argument".  */
  976.   if (struct_return)
  977.     {
  978.       store_unsigned_integer (buf, 8, byte_order, struct_addr);
  979.       regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
  980.     }

  982.   /* Store return address.  */
  983.   sp -= 8;
  984.   store_unsigned_integer (buf, 8, byte_order, bp_addr);
  985.   write_memory (sp, buf, 8);

  987.   /* Finally, update the stack pointer...  */
  988.   store_unsigned_integer (buf, 8, byte_order, sp);
  989.   regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);

  991.   /* ...and fake a frame pointer.  */
  992.   regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);

  994.   return sp + 16;
  995. }

  997. /* Displaced instruction handling.  */

  999. /* A partially decoded instruction.
  1000.    This contains enough details for displaced stepping purposes.  */

  1002. ‌struct amd64_insn
  1003. {
  1004.   /* The number of opcode bytes.  */
  1005.   int opcode_len;
  1006.   /* The offset of the rex prefix or -1 if not present.  */
  1007.   int rex_offset;
  1008.   /* The offset to the first opcode byte.  */
  1009.   int opcode_offset;
  1010.   /* The offset to the modrm byte or -1 if not present.  */
  1011.   int modrm_offset;

  1013.   /* The raw instruction.  */
  1014.   gdb_byte *raw_insn;
  1015. };

  1017. ‌struct displaced_step_closure
  1018. {
  1019.   /* For rip-relative insns, saved copy of the reg we use instead of %rip.  */
  1020.   int tmp_used;
  1021.   int tmp_regno;
  1022.   ULONGEST tmp_save;

  1024.   /* Details of the instruction.  */
  1025.   struct amd64_insn insn_details;

  1027.   /* Amount of space allocated to insn_buf.  */
  1028.   int max_len;

  1030.   /* The possibly modified insn.
  1031.      This is a variable-length field.  */
  1032.   gdb_byte insn_buf[1];
  1033. };

  1035. /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
  1036.    ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
  1037.    at which point delete these in favor of libopcodes' versions).  */

  1039. ‌static const unsigned char onebyte_has_modrm[256] = {
  1040.   /*           0 1 2 3 4 5 6 7 8 9 a b c d e f          */
  1041.   /*           -------------------------------          */
  1042.   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
  1043.   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
  1044.   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
  1045.   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
  1046.   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
  1047.   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
  1048.   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
  1049.   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
  1050.   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
  1051.   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
  1052.   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
  1053.   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
  1054.   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
  1055.   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
  1056.   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
  1057.   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
  1058.   /*           -------------------------------          */
  1059.   /*           0 1 2 3 4 5 6 7 8 9 a b c d e f          */
  1060. };

  1062. ‌static const unsigned char twobyte_has_modrm[256] = {
  1063.   /*           0 1 2 3 4 5 6 7 8 9 a b c d e f          */
  1064.   /*           -------------------------------          */
  1065.   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
  1066.   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
  1067.   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
  1068.   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
  1069.   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
  1070.   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
  1071.   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
  1072.   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
  1073.   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
  1074.   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
  1075.   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
  1076.   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
  1077.   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
  1078.   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
  1079.   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
  1080.   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
  1081.   /*           -------------------------------          */
  1082.   /*           0 1 2 3 4 5 6 7 8 9 a b c d e f          */
  1083. };

  1085. static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);

  1087. static int
  1088. ‌rex_prefix_p (gdb_byte pfx)
  1089. {
  1090.   return REX_PREFIX_P (pfx);
  1091. }

  1093. /* Skip the legacy instruction prefixes in INSN.
  1094.    We assume INSN is properly sentineled so we don't have to worry
  1095.    about falling off the end of the buffer.  */

  1097. static gdb_byte *
  1098. ‌amd64_skip_prefixes (gdb_byte *insn)
  1099. {
  1100.   while (1)
  1101.     {
  1102.       switch (*insn)
  1103.         {
  1104.         case DATA_PREFIX_OPCODE:
  1105.         case ADDR_PREFIX_OPCODE:
  1106.         case CS_PREFIX_OPCODE:
  1107.         case DS_PREFIX_OPCODE:
  1108.         case ES_PREFIX_OPCODE:
  1109.         case FS_PREFIX_OPCODE:
  1110.         case GS_PREFIX_OPCODE:
  1111.         case SS_PREFIX_OPCODE:
  1112.         case LOCK_PREFIX_OPCODE:
  1113.         case REPE_PREFIX_OPCODE:
  1114.         case REPNE_PREFIX_OPCODE:
  1115.           ++insn;
  1116.           continue;
  1117.         default:
  1118.           break;
  1119.         }
  1120.       break;
  1121.     }

  1123.   return insn;
  1124. }

  1126. /* Return an integer register (other than RSP) that is unused as an input
  1127.    operand in INSN.
  1128.    In order to not require adding a rex prefix if the insn doesn't already
  1129.    have one, the result is restricted to RAX ... RDI, sans RSP.
  1130.    The register numbering of the result follows architecture ordering,
  1131.    e.g. RDI = 7.  */

  1133. static int
  1134. ‌amd64_get_unused_input_int_reg (const struct amd64_insn *details)
  1135. {
  1136.   /* 1 bit for each reg */
  1137.   int used_regs_mask = 0;

  1139.   /* There can be at most 3 int regs used as inputs in an insn, and we have
  1140.      7 to choose from (RAX ... RDI, sans RSP).
  1141.      This allows us to take a conservative approach and keep things simple.
  1142.      E.g. By avoiding RAX, we don't have to specifically watch for opcodes
  1143.      that implicitly specify RAX.  */

  1145.   /* Avoid RAX.  */
  1146.   used_regs_mask |= 1 << EAX_REG_NUM;
  1147.   /* Similarily avoid RDX, implicit operand in divides.  */
  1148.   used_regs_mask |= 1 << EDX_REG_NUM;
  1149.   /* Avoid RSP.  */
  1150.   used_regs_mask |= 1 << ESP_REG_NUM;

  1152.   /* If the opcode is one byte long and there's no ModRM byte,
  1153.      assume the opcode specifies a register.  */
  1154.   if (details->opcode_len == 1 && details->modrm_offset == -1)
  1155.     used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);

  1157.   /* Mark used regs in the modrm/sib bytes.  */
  1158.   if (details->modrm_offset != -1)
  1159.     {
  1160.       int modrm = details->raw_insn[details->modrm_offset];
  1161.       int mod = MODRM_MOD_FIELD (modrm);
  1162.       int reg = MODRM_REG_FIELD (modrm);
  1163.       int rm = MODRM_RM_FIELD (modrm);
  1164.       int have_sib = mod != 3 && rm == 4;

  1166.       /* Assume the reg field of the modrm byte specifies a register.  */
  1167.       used_regs_mask |= 1 << reg;

  1169.       if (have_sib)
  1170.         {
  1171.           int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
  1172.           int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
  1173.           used_regs_mask |= 1 << base;
  1174.           used_regs_mask |= 1 << idx;
  1175.         }
  1176.       else
  1177.         {
  1178.           used_regs_mask |= 1 << rm;
  1179.         }
  1180.     }

  1182.   gdb_assert (used_regs_mask < 256);
  1183.   gdb_assert (used_regs_mask != 255);

  1185.   /* Finally, find a free reg.  */
  1186.   {
  1187.     int i;

  1189.     for (i = 0; i < 8; ++i)
  1190.       {
  1191.         if (! (used_regs_mask & (1 << i)))
  1192.           return i;
  1193.       }

  1195.     /* We shouldn't get here.  */
  1196.     internal_error (__FILE__, __LINE__, _("unable to find free reg"));
  1197.   }
  1198. }

  1200. /* Extract the details of INSN that we need.  */

  1202. static void
  1203. ‌amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
  1204. {
  1205.   gdb_byte *start = insn;
  1206.   int need_modrm;

  1208.   details->raw_insn = insn;

  1210.   details->opcode_len = -1;
  1211.   details->rex_offset = -1;
  1212.   details->opcode_offset = -1;
  1213.   details->modrm_offset = -1;

  1215.   /* Skip legacy instruction prefixes.  */
  1216.   insn = amd64_skip_prefixes (insn);

  1218.   /* Skip REX instruction prefix.  */
  1219.   if (rex_prefix_p (*insn))
  1220.     {
  1221.       details->rex_offset = insn - start;
  1222.       ++insn;
  1223.     }

  1225.   details->opcode_offset = insn - start;

  1227.   if (*insn == TWO_BYTE_OPCODE_ESCAPE)
  1228.     {
  1229.       /* Two or three-byte opcode.  */
  1230.       ++insn;
  1231.       need_modrm = twobyte_has_modrm[*insn];

  1233.       /* Check for three-byte opcode.  */
  1234.       switch (*insn)
  1235.         {
  1236.         case 0x24:
  1237.         case 0x25:
  1238.         case 0x38:
  1239.         case 0x3a:
  1240.         case 0x7a:
  1241.         case 0x7b:
  1242.           ++insn;
  1243.           details->opcode_len = 3;
  1244.           break;
  1245.         default:
  1246.           details->opcode_len = 2;
  1247.           break;
  1248.         }
  1249.     }
  1250.   else
  1251.     {
  1252.       /* One-byte opcode.  */
  1253.       need_modrm = onebyte_has_modrm[*insn];
  1254.       details->opcode_len = 1;
  1255.     }

  1257.   if (need_modrm)
  1258.     {
  1259.       ++insn;
  1260.       details->modrm_offset = insn - start;
  1261.     }
  1262. }

  1264. /* Update %rip-relative addressing in INSN.

  1266.    %rip-relative addressing only uses a 32-bit displacement.
  1267.    32 bits is not enough to be guaranteed to cover the distance between where
  1268.    the real instruction is and where its copy is.
  1269.    Convert the insn to use base+disp addressing.
  1270.    We set base = pc + insn_length so we can leave disp unchanged.  */

  1272. static void
  1273. ‌fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
  1274.               CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
  1275. {
  1276.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1277.   const struct amd64_insn *insn_details = &dsc->insn_details;
  1278.   int modrm_offset = insn_details->modrm_offset;
  1279.   gdb_byte *insn = insn_details->raw_insn + modrm_offset;
  1280.   CORE_ADDR rip_base;
  1281.   int32_t disp;
  1282.   int insn_length;
  1283.   int arch_tmp_regno, tmp_regno;
  1284.   ULONGEST orig_value;

  1286.   /* %rip+disp32 addressing mode, displacement follows ModRM byte.  */
  1287.   ++insn;

  1289.   /* Compute the rip-relative address.        */
  1290.   disp = extract_signed_integer (insn, sizeof (int32_t), byte_order);
  1291.   insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
  1292.                                           dsc->max_len, from);
  1293.   rip_base = from + insn_length;

  1295.   /* We need a register to hold the address.
  1296.      Pick one not used in the insn.
  1297.      NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7.  */
  1298.   arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
  1299.   tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);

  1301.   /* REX.B should be unset as we were using rip-relative addressing,
  1302.      but ensure it's unset anyway, tmp_regno is not r8-r15.  */
  1303.   if (insn_details->rex_offset != -1)
  1304.     dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;

  1306.   regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
  1307.   dsc->tmp_regno = tmp_regno;
  1308.   dsc->tmp_save = orig_value;
  1309.   dsc->tmp_used = 1;

  1311.   /* Convert the ModRM field to be base+disp.  */
  1312.   dsc->insn_buf[modrm_offset] &= ~0xc7;
  1313.   dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;

  1315.   regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);

  1317.   if (debug_displaced)
  1318.     fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
  1319.                         "displaced: using temp reg %d, old value %s, new value %s\n",
  1320.                         dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
  1321.                         paddress (gdbarch, rip_base));
  1322. }

  1324. static void
  1325. ‌fixup_displaced_copy (struct gdbarch *gdbarch,
  1326.                       struct displaced_step_closure *dsc,
  1327.                       CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
  1328. {
  1329.   const struct amd64_insn *details = &dsc->insn_details;

  1331.   if (details->modrm_offset != -1)
  1332.     {
  1333.       gdb_byte modrm = details->raw_insn[details->modrm_offset];

  1335.       if ((modrm & 0xc7) == 0x05)
  1336.         {
  1337.           /* The insn uses rip-relative addressing.
  1338.              Deal with it.  */
  1339.           fixup_riprel (gdbarch, dsc, from, to, regs);
  1340.         }
  1341.     }
  1342. }

  1344. struct displaced_step_closure *
  1345. ‌amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
  1346.                                 CORE_ADDR from, CORE_ADDR to,
  1347.                                 struct regcache *regs)
  1348. {
  1349.   int len = gdbarch_max_insn_length (gdbarch);
  1350.   /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
  1351.      continually watch for running off the end of the buffer.  */
  1352.   int fixup_sentinel_space = len;
  1353.   struct displaced_step_closure *dsc =
  1354.     xmalloc (sizeof (*dsc) + len + fixup_sentinel_space);
  1355.   gdb_byte *buf = &dsc->insn_buf[0];
  1356.   struct amd64_insn *details = &dsc->insn_details;

  1358.   dsc->tmp_used = 0;
  1359.   dsc->max_len = len + fixup_sentinel_space;

  1361.   read_memory (from, buf, len);

  1363.   /* Set up the sentinel space so we don't have to worry about running
  1364.      off the end of the buffer.  An excessive number of leading prefixes
  1365.      could otherwise cause this.  */
  1366.   memset (buf + len, 0, fixup_sentinel_space);

  1368.   amd64_get_insn_details (buf, details);

  1370.   /* GDB may get control back after the insn after the syscall.
  1371.      Presumably this is a kernel bug.
  1372.      If this is a syscall, make sure there's a nop afterwards.  */
  1373.   {
  1374.     int syscall_length;

  1376.     if (amd64_syscall_p (details, &syscall_length))
  1377.       buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
  1378.   }

  1380.   /* Modify the insn to cope with the address where it will be executed from.
  1381.      In particular, handle any rip-relative addressing.         */
  1382.   fixup_displaced_copy (gdbarch, dsc, from, to, regs);

  1384.   write_memory (to, buf, len);

  1386.   if (debug_displaced)
  1387.     {
  1388.       fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
  1389.                           paddress (gdbarch, from), paddress (gdbarch, to));
  1390.       displaced_step_dump_bytes (gdb_stdlog, buf, len);
  1391.     }

  1393.   return dsc;
  1394. }

  1396. static int
  1397. ‌amd64_absolute_jmp_p (const struct amd64_insn *details)
  1398. {
  1399.   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];

  1401.   if (insn[0] == 0xff)
  1402.     {
  1403.       /* jump near, absolute indirect (/4) */
  1404.       if ((insn[1] & 0x38) == 0x20)
  1405.         return 1;

  1407.       /* jump far, absolute indirect (/5) */
  1408.       if ((insn[1] & 0x38) == 0x28)
  1409.         return 1;
  1410.     }

  1412.   return 0;
  1413. }

  1415. /* Return non-zero if the instruction DETAILS is a jump, zero otherwise.  */

  1417. static int
  1418. ‌amd64_jmp_p (const struct amd64_insn *details)
  1419. {
  1420.   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];

  1422.   /* jump short, relative.  */
  1423.   if (insn[0] == 0xeb)
  1424.     return 1;

  1426.   /* jump near, relative.  */
  1427.   if (insn[0] == 0xe9)
  1428.     return 1;

  1430.   return amd64_absolute_jmp_p (details);
  1431. }

  1433. static int
  1434. ‌amd64_absolute_call_p (const struct amd64_insn *details)
  1435. {
  1436.   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];

  1438.   if (insn[0] == 0xff)
  1439.     {
  1440.       /* Call near, absolute indirect (/2) */
  1441.       if ((insn[1] & 0x38) == 0x10)
  1442.         return 1;

  1444.       /* Call far, absolute indirect (/3) */
  1445.       if ((insn[1] & 0x38) == 0x18)
  1446.         return 1;
  1447.     }

  1449.   return 0;
  1450. }

  1452. static int
  1453. ‌amd64_ret_p (const struct amd64_insn *details)
  1454. {
  1455.   /* NOTE: gcc can emit "repz ; ret".  */
  1456.   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];

  1458.   switch (insn[0])
  1459.     {
  1460.     case 0xc2: /* ret near, pop N bytes */
  1461.     case 0xc3: /* ret near */
  1462.     case 0xca: /* ret far, pop N bytes */
  1463.     case 0xcb: /* ret far */
  1464.     case 0xcf: /* iret */
  1465.       return 1;

  1467.     default:
  1468.       return 0;
  1469.     }
  1470. }

  1472. static int
  1473. ‌amd64_call_p (const struct amd64_insn *details)
  1474. {
  1475.   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];

  1477.   if (amd64_absolute_call_p (details))
  1478.     return 1;

  1480.   /* call near, relative */
  1481.   if (insn[0] == 0xe8)
  1482.     return 1;

  1484.   return 0;
  1485. }

  1487. /* Return non-zero if INSN is a system call, and set *LENGTHP to its
  1488.    length in bytes.  Otherwise, return zero.  */

  1490. static int
  1491. ‌amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
  1492. {
  1493.   const gdb_byte *insn = &details->raw_insn[details->opcode_offset];

  1495.   if (insn[0] == 0x0f && insn[1] == 0x05)
  1496.     {
  1497.       *lengthp = 2;
  1498.       return 1;
  1499.     }

  1501.   return 0;
  1502. }

  1504. /* Classify the instruction at ADDR using PRED.
  1505.    Throw an error if the memory can't be read.  */

  1507. static int
  1508. ‌amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
  1509.                         int (*pred) (const struct amd64_insn *))
  1510. {
  1511.   struct amd64_insn details;
  1512.   gdb_byte *buf;
  1513.   int len, classification;

  1515.   len = gdbarch_max_insn_length (gdbarch);
  1516.   buf = alloca (len);

  1518.   read_code (addr, buf, len);
  1519.   amd64_get_insn_details (buf, &details);

  1521.   classification = pred (&details);

  1523.   return classification;
  1524. }

  1526. /* The gdbarch insn_is_call method.  */

  1528. static int
  1529. ‌amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
  1530. {
  1531.   return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
  1532. }

  1534. /* The gdbarch insn_is_ret method.  */

  1536. static int
  1537. ‌amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
  1538. {
  1539.   return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
  1540. }

  1542. /* The gdbarch insn_is_jump method.  */

  1544. static int
  1545. ‌amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
  1546. {
  1547.   return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
  1548. }

  1550. /* Fix up the state of registers and memory after having single-stepped
  1551.    a displaced instruction.  */

  1553. void
  1554. ‌amd64_displaced_step_fixup (struct gdbarch *gdbarch,
  1555.                             struct displaced_step_closure *dsc,
  1556.                             CORE_ADDR from, CORE_ADDR to,
  1557.                             struct regcache *regs)
  1558. {
  1559.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1560.   /* The offset we applied to the instruction's address.  */
  1561.   ULONGEST insn_offset = to - from;
  1562.   gdb_byte *insn = dsc->insn_buf;
  1563.   const struct amd64_insn *insn_details = &dsc->insn_details;

  1565.   if (debug_displaced)
  1566.     fprintf_unfiltered (gdb_stdlog,
  1567.                         "displaced: fixup (%s, %s), "
  1568.                         "insn = 0x%02x 0x%02x ...\n",
  1569.                         paddress (gdbarch, from), paddress (gdbarch, to),
  1570.                         insn[0], insn[1]);

  1572.   /* If we used a tmp reg, restore it.        */

  1574.   if (dsc->tmp_used)
  1575.     {
  1576.       if (debug_displaced)
  1577.         fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
  1578.                             dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
  1579.       regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
  1580.     }

  1582.   /* The list of issues to contend with here is taken from
  1583.      resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
  1584.      Yay for Free Software!  */

  1586.   /* Relocate the %rip back to the program's instruction stream,
  1587.      if necessary.  */

  1589.   /* Except in the case of absolute or indirect jump or call
  1590.      instructions, or a return instruction, the new rip is relative to
  1591.      the displaced instruction; make it relative to the original insn.
  1592.      Well, signal handler returns don't need relocation either, but we use the
  1593.      value of %rip to recognize those; see below.  */
  1594.   if (! amd64_absolute_jmp_p (insn_details)
  1595.       && ! amd64_absolute_call_p (insn_details)
  1596.       && ! amd64_ret_p (insn_details))
  1597.     {
  1598.       ULONGEST orig_rip;
  1599.       int insn_len;

  1601.       regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);

  1603.       /* A signal trampoline system call changes the %rip, resuming
  1604.          execution of the main program after the signal handler has
  1605.          returned.  That makes them like 'return' instructions; we
  1606.          shouldn't relocate %rip.

  1608.          But most system calls don't, and we do need to relocate %rip.

  1610.          Our heuristic for distinguishing these cases: if stepping
  1611.          over the system call instruction left control directly after
  1612.          the instruction, the we relocate --- control almost certainly
  1613.          doesn't belong in the displaced copy.        Otherwise, we assume
  1614.          the instruction has put control where it belongs, and leave
  1615.          it unrelocated.  Goodness help us if there are PC-relative
  1616.          system calls.        */
  1617.       if (amd64_syscall_p (insn_details, &insn_len)
  1618.           && orig_rip != to + insn_len
  1619.           /* GDB can get control back after the insn after the syscall.
  1620.              Presumably this is a kernel bug.
  1621.              Fixup ensures its a nop, we add one to the length for it.  */
  1622.           && orig_rip != to + insn_len + 1)
  1623.         {
  1624.           if (debug_displaced)
  1625.             fprintf_unfiltered (gdb_stdlog,
  1626.                                 "displaced: syscall changed %%rip; "
  1627.                                 "not relocating\n");
  1628.         }
  1629.       else
  1630.         {
  1631.           ULONGEST rip = orig_rip - insn_offset;

  1633.           /* If we just stepped over a breakpoint insn, we don't backup
  1634.              the pc on purpose; this is to match behaviour without
  1635.              stepping.  */

  1637.           regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);

  1639.           if (debug_displaced)
  1640.             fprintf_unfiltered (gdb_stdlog,
  1641.                                 "displaced: "
  1642.                                 "relocated %%rip from %s to %s\n",
  1643.                                 paddress (gdbarch, orig_rip),
  1644.                                 paddress (gdbarch, rip));
  1645.         }
  1646.     }

  1648.   /* If the instruction was PUSHFL, then the TF bit will be set in the
  1649.      pushed value, and should be cleared.  We'll leave this for later,
  1650.      since GDB already messes up the TF flag when stepping over a
  1651.      pushfl.  */

  1653.   /* If the instruction was a call, the return address now atop the
  1654.      stack is the address following the copied instruction.  We need
  1655.      to make it the address following the original instruction.         */
  1656.   if (amd64_call_p (insn_details))
  1657.     {
  1658.       ULONGEST rsp;
  1659.       ULONGEST retaddr;
  1660.       const ULONGEST retaddr_len = 8;

  1662.       regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
  1663.       retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
  1664.       retaddr = (retaddr - insn_offset) & 0xffffffffUL;
  1665.       write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);

  1667.       if (debug_displaced)
  1668.         fprintf_unfiltered (gdb_stdlog,
  1669.                             "displaced: relocated return addr at %s "
  1670.                             "to %s\n",
  1671.                             paddress (gdbarch, rsp),
  1672.                             paddress (gdbarch, retaddr));
  1673.     }
  1674. }

  1676. /* If the instruction INSN uses RIP-relative addressing, return the
  1677.    offset into the raw INSN where the displacement to be adjusted is
  1678.    found.  Returns 0 if the instruction doesn't use RIP-relative
  1679.    addressing.  */

  1681. static int
  1682. ‌rip_relative_offset (struct amd64_insn *insn)
  1683. {
  1684.   if (insn->modrm_offset != -1)
  1685.     {
  1686.       gdb_byte modrm = insn->raw_insn[insn->modrm_offset];

  1688.       if ((modrm & 0xc7) == 0x05)
  1689.         {
  1690.           /* The displacement is found right after the ModRM byte.  */
  1691.           return insn->modrm_offset + 1;
  1692.         }
  1693.     }

  1695.   return 0;
  1696. }

  1698. static void
  1699. ‌append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
  1700. {
  1701.   target_write_memory (*to, buf, len);
  1702.   *to += len;
  1703. }

  1705. static void
  1706. ‌amd64_relocate_instruction (struct gdbarch *gdbarch,
  1707.                             CORE_ADDR *to, CORE_ADDR oldloc)
  1708. {
  1709.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1710.   int len = gdbarch_max_insn_length (gdbarch);
  1711.   /* Extra space for sentinels.  */
  1712.   int fixup_sentinel_space = len;
  1713.   gdb_byte *buf = xmalloc (len + fixup_sentinel_space);
  1714.   struct amd64_insn insn_details;
  1715.   int offset = 0;
  1716.   LONGEST rel32, newrel;
  1717.   gdb_byte *insn;
  1718.   int insn_length;

  1720.   read_memory (oldloc, buf, len);

  1722.   /* Set up the sentinel space so we don't have to worry about running
  1723.      off the end of the buffer.  An excessive number of leading prefixes
  1724.      could otherwise cause this.  */
  1725.   memset (buf + len, 0, fixup_sentinel_space);

  1727.   insn = buf;
  1728.   amd64_get_insn_details (insn, &insn_details);

  1730.   insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);

  1732.   /* Skip legacy instruction prefixes.  */
  1733.   insn = amd64_skip_prefixes (insn);

  1735.   /* Adjust calls with 32-bit relative addresses as push/jump, with
  1736.      the address pushed being the location where the original call in
  1737.      the user program would return to.  */
  1738.   if (insn[0] == 0xe8)
  1739.     {
  1740.       gdb_byte push_buf[16];
  1741.       unsigned int ret_addr;

  1743.       /* Where "ret" in the original code will return to.  */
  1744.       ret_addr = oldloc + insn_length;
  1745.       push_buf[0] = 0x68; /* pushq $...  */
  1746.       store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
  1747.       /* Push the push.  */
  1748.       append_insns (to, 5, push_buf);

  1750.       /* Convert the relative call to a relative jump.  */
  1751.       insn[0] = 0xe9;

  1753.       /* Adjust the destination offset.  */
  1754.       rel32 = extract_signed_integer (insn + 1, 4, byte_order);
  1755.       newrel = (oldloc - *to) + rel32;
  1756.       store_signed_integer (insn + 1, 4, byte_order, newrel);

  1758.       if (debug_displaced)
  1759.         fprintf_unfiltered (gdb_stdlog,
  1760.                             "Adjusted insn rel32=%s at %s to"
  1761.                             " rel32=%s at %s\n",
  1762.                             hex_string (rel32), paddress (gdbarch, oldloc),
  1763.                             hex_string (newrel), paddress (gdbarch, *to));

  1765.       /* Write the adjusted jump into its displaced location.  */
  1766.       append_insns (to, 5, insn);
  1767.       return;
  1768.     }

  1770.   offset = rip_relative_offset (&insn_details);
  1771.   if (!offset)
  1772.     {
  1773.       /* Adjust jumps with 32-bit relative addresses.  Calls are
  1774.          already handled above.  */
  1775.       if (insn[0] == 0xe9)
  1776.         offset = 1;
  1777.       /* Adjust conditional jumps.  */
  1778.       else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
  1779.         offset = 2;
  1780.     }

  1782.   if (offset)
  1783.     {
  1784.       rel32 = extract_signed_integer (insn + offset, 4, byte_order);
  1785.       newrel = (oldloc - *to) + rel32;
  1786.       store_signed_integer (insn + offset, 4, byte_order, newrel);
  1787.       if (debug_displaced)
  1788.         fprintf_unfiltered (gdb_stdlog,
  1789.                             "Adjusted insn rel32=%s at %s to"
  1790.                             " rel32=%s at %s\n",
  1791.                             hex_string (rel32), paddress (gdbarch, oldloc),
  1792.                             hex_string (newrel), paddress (gdbarch, *to));
  1793.     }

  1795.   /* Write the adjusted instruction into its displaced location.  */
  1796.   append_insns (to, insn_length, buf);
  1797. }


  1800. /* The maximum number of saved registers.  This should include %rip.  */
  1801. ‌#define AMD64_NUM_SAVED_REGS        AMD64_NUM_GREGS

  1803. ‌struct amd64_frame_cache
  1804. {
  1805.   /* Base address.  */
  1806.   CORE_ADDR base;
  1807.   int base_p;
  1808.   CORE_ADDR sp_offset;
  1809.   CORE_ADDR pc;

  1811.   /* Saved registers.  */
  1812.   CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
  1813.   CORE_ADDR saved_sp;
  1814.   int saved_sp_reg;

  1816.   /* Do we have a frame?  */
  1817.   int frameless_p;
  1818. };

  1820. /* Initialize a frame cache.  */

  1822. static void
  1823. ‌amd64_init_frame_cache (struct amd64_frame_cache *cache)
  1824. {
  1825.   int i;

  1827.   /* Base address.  */
  1828.   cache->base = 0;
  1829.   cache->base_p = 0;
  1830.   cache->sp_offset = -8;
  1831.   cache->pc = 0;

  1833.   /* Saved registers.  We initialize these to -1 since zero is a valid
  1834.      offset (that's where %rbp is supposed to be stored).
  1835.      The values start out as being offsets, and are later converted to
  1836.      addresses (at which point -1 is interpreted as an address, still meaning
  1837.      "invalid").  */
  1838.   for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
  1839.     cache->saved_regs[i] = -1;
  1840.   cache->saved_sp = 0;
  1841.   cache->saved_sp_reg = -1;

  1843.   /* Frameless until proven otherwise.  */
  1844.   cache->frameless_p = 1;
  1845. }

  1847. /* Allocate and initialize a frame cache.  */

  1849. static struct amd64_frame_cache *
  1850. ‌amd64_alloc_frame_cache (void)
  1851. {
  1852.   struct amd64_frame_cache *cache;

  1854.   cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
  1855.   amd64_init_frame_cache (cache);
  1856.   return cache;
  1857. }

  1859. /* GCC 4.4 and later, can put code in the prologue to realign the
  1860.    stack pointer.  Check whether PC points to such code, and update
  1861.    CACHE accordingly.  Return the first instruction after the code
  1862.    sequence or CURRENT_PC, whichever is smaller.  If we don't
  1863.    recognize the code, return PC.  */

  1865. static CORE_ADDR
  1866. ‌amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
  1867.                            struct amd64_frame_cache *cache)
  1868. {
  1869.   /* There are 2 code sequences to re-align stack before the frame
  1870.      gets set up:

  1872.         1. Use a caller-saved saved register:

  1874.                 leaq  8(%rsp), %reg
  1875.                 andq  $-XXX, %rsp
  1876.                 pushq -8(%reg)

  1878.         2. Use a callee-saved saved register:

  1880.                 pushq %reg
  1881.                 leaq  16(%rsp), %reg
  1882.                 andq  $-XXX, %rsp
  1883.                 pushq -8(%reg)

  1885.      "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:

  1887.              0x48 0x83 0xe4 0xf0                        andq $-16, %rsp
  1888.              0x48 0x81 0xe4 0x00 0xff 0xff 0xff        andq $-256, %rsp
  1889.    */

  1891.   gdb_byte buf[18];
  1892.   int reg, r;
  1893.   int offset, offset_and;

  1895.   if (target_read_code (pc, buf, sizeof buf))
  1896.     return pc;

  1898.   /* Check caller-saved saved register.  The first instruction has
  1899.      to be "leaq 8(%rsp), %reg".  */
  1900.   if ((buf[0] & 0xfb) == 0x48
  1901.       && buf[1] == 0x8d
  1902.       && buf[3] == 0x24
  1903.       && buf[4] == 0x8)
  1904.     {
  1905.       /* MOD must be binary 10 and R/M must be binary 100.  */
  1906.       if ((buf[2] & 0xc7) != 0x44)
  1907.         return pc;

  1909.       /* REG has register number.  */
  1910.       reg = (buf[2] >> 3) & 7;

  1912.       /* Check the REX.R bit.  */
  1913.       if (buf[0] == 0x4c)
  1914.         reg += 8;

  1916.       offset = 5;
  1917.     }
  1918.   else
  1919.     {
  1920.       /* Check callee-saved saved register.  The first instruction
  1921.          has to be "pushq %reg".  */
  1922.       reg = 0;
  1923.       if ((buf[0] & 0xf8) == 0x50)
  1924.         offset = 0;
  1925.       else if ((buf[0] & 0xf6) == 0x40
  1926.                && (buf[1] & 0xf8) == 0x50)
  1927.         {
  1928.           /* Check the REX.B bit.  */
  1929.           if ((buf[0] & 1) != 0)
  1930.             reg = 8;

  1932.           offset = 1;
  1933.         }
  1934.       else
  1935.         return pc;

  1937.       /* Get register.  */
  1938.       reg += buf[offset] & 0x7;

  1940.       offset++;

  1942.       /* The next instruction has to be "leaq 16(%rsp), %reg".  */
  1943.       if ((buf[offset] & 0xfb) != 0x48
  1944.           || buf[offset + 1] != 0x8d
  1945.           || buf[offset + 3] != 0x24
  1946.           || buf[offset + 4] != 0x10)
  1947.         return pc;

  1949.       /* MOD must be binary 10 and R/M must be binary 100.  */
  1950.       if ((buf[offset + 2] & 0xc7) != 0x44)
  1951.         return pc;

  1953.       /* REG has register number.  */
  1954.       r = (buf[offset + 2] >> 3) & 7;

  1956.       /* Check the REX.R bit.  */
  1957.       if (buf[offset] == 0x4c)
  1958.         r += 8;

  1960.       /* Registers in pushq and leaq have to be the same.  */
  1961.       if (reg != r)
  1962.         return pc;

  1964.       offset += 5;
  1965.     }

  1967.   /* Rigister can't be %rsp nor %rbp.  */
  1968.   if (reg == 4 || reg == 5)
  1969.     return pc;

  1971.   /* The next instruction has to be "andq $-XXX, %rsp".  */
  1972.   if (buf[offset] != 0x48
  1973.       || buf[offset + 2] != 0xe4
  1974.       || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
  1975.     return pc;

  1977.   offset_and = offset;
  1978.   offset += buf[offset + 1] == 0x81 ? 7 : 4;

  1980.   /* The next instruction has to be "pushq -8(%reg)".  */
  1981.   r = 0;
  1982.   if (buf[offset] == 0xff)
  1983.     offset++;
  1984.   else if ((buf[offset] & 0xf6) == 0x40
  1985.            && buf[offset + 1] == 0xff)
  1986.     {
  1987.       /* Check the REX.B bit.  */
  1988.       if ((buf[offset] & 0x1) != 0)
  1989.         r = 8;
  1990.       offset += 2;
  1991.     }
  1992.   else
  1993.     return pc;

  1995.   /* 8bit -8 is 0xf8.  REG must be binary 110 and MOD must be binary
  1996.      01.  */
  1997.   if (buf[offset + 1] != 0xf8
  1998.       || (buf[offset] & 0xf8) != 0x70)
  1999.     return pc;

  2001.   /* R/M has register.  */
  2002.   r += buf[offset] & 7;

  2004.   /* Registers in leaq and pushq have to be the same.  */
  2005.   if (reg != r)
  2006.     return pc;

  2008.   if (current_pc > pc + offset_and)
  2009.     cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);

  2011.   return min (pc + offset + 2, current_pc);
  2012. }

  2014. /* Similar to amd64_analyze_stack_align for x32.  */

  2016. static CORE_ADDR
  2017. ‌amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
  2018.                                struct amd64_frame_cache *cache)
  2019. {
  2020.   /* There are 2 code sequences to re-align stack before the frame
  2021.      gets set up:

  2023.         1. Use a caller-saved saved register:

  2025.                 leaq  8(%rsp), %reg
  2026.                 andq  $-XXX, %rsp
  2027.                 pushq -8(%reg)

  2029.            or

  2031.                 [addr32] leal  8(%rsp), %reg
  2032.                 andl  $-XXX, %esp
  2033.                 [addr32] pushq -8(%reg)

  2035.         2. Use a callee-saved saved register:

  2037.                 pushq %reg
  2038.                 leaq  16(%rsp), %reg
  2039.                 andq  $-XXX, %rsp
  2040.                 pushq -8(%reg)

  2042.            or

  2044.                 pushq %reg
  2045.                 [addr32] leal  16(%rsp), %reg
  2046.                 andl  $-XXX, %esp
  2047.                 [addr32] pushq -8(%reg)

  2049.      "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:

  2051.              0x48 0x83 0xe4 0xf0                        andq $-16, %rsp
  2052.              0x48 0x81 0xe4 0x00 0xff 0xff 0xff        andq $-256, %rsp

  2054.      "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:

  2056.              0x83 0xe4 0xf0                        andl $-16, %esp
  2057.              0x81 0xe4 0x00 0xff 0xff 0xff        andl $-256, %esp
  2058.    */

  2060.   gdb_byte buf[19];
  2061.   int reg, r;
  2062.   int offset, offset_and;

  2064.   if (target_read_memory (pc, buf, sizeof buf))
  2065.     return pc;

  2067.   /* Skip optional addr32 prefix.  */
  2068.   offset = buf[0] == 0x67 ? 1 : 0;

  2070.   /* Check caller-saved saved register.  The first instruction has
  2071.      to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg".  */
  2072.   if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
  2073.       && buf[offset + 1] == 0x8d
  2074.       && buf[offset + 3] == 0x24
  2075.       && buf[offset + 4] == 0x8)
  2076.     {
  2077.       /* MOD must be binary 10 and R/M must be binary 100.  */
  2078.       if ((buf[offset + 2] & 0xc7) != 0x44)
  2079.         return pc;

  2081.       /* REG has register number.  */
  2082.       reg = (buf[offset + 2] >> 3) & 7;

  2084.       /* Check the REX.R bit.  */
  2085.       if ((buf[offset] & 0x4) != 0)
  2086.         reg += 8;

  2088.       offset += 5;
  2089.     }
  2090.   else
  2091.     {
  2092.       /* Check callee-saved saved register.  The first instruction
  2093.          has to be "pushq %reg".  */
  2094.       reg = 0;
  2095.       if ((buf[offset] & 0xf6) == 0x40
  2096.           && (buf[offset + 1] & 0xf8) == 0x50)
  2097.         {
  2098.           /* Check the REX.B bit.  */
  2099.           if ((buf[offset] & 1) != 0)
  2100.             reg = 8;

  2102.           offset += 1;
  2103.         }
  2104.       else if ((buf[offset] & 0xf8) != 0x50)
  2105.         return pc;

  2107.       /* Get register.  */
  2108.       reg += buf[offset] & 0x7;

  2110.       offset++;

  2112.       /* Skip optional addr32 prefix.  */
  2113.       if (buf[offset] == 0x67)
  2114.         offset++;

  2116.       /* The next instruction has to be "leaq 16(%rsp), %reg" or
  2117.          "leal 16(%rsp), %reg".  */
  2118.       if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
  2119.           || buf[offset + 1] != 0x8d
  2120.           || buf[offset + 3] != 0x24
  2121.           || buf[offset + 4] != 0x10)
  2122.         return pc;

  2124.       /* MOD must be binary 10 and R/M must be binary 100.  */
  2125.       if ((buf[offset + 2] & 0xc7) != 0x44)
  2126.         return pc;

  2128.       /* REG has register number.  */
  2129.       r = (buf[offset + 2] >> 3) & 7;

  2131.       /* Check the REX.R bit.  */
  2132.       if ((buf[offset] & 0x4) != 0)
  2133.         r += 8;

  2135.       /* Registers in pushq and leaq have to be the same.  */
  2136.       if (reg != r)
  2137.         return pc;

  2139.       offset += 5;
  2140.     }

  2142.   /* Rigister can't be %rsp nor %rbp.  */
  2143.   if (reg == 4 || reg == 5)
  2144.     return pc;

  2146.   /* The next instruction may be "andq $-XXX, %rsp" or
  2147.      "andl $-XXX, %esp".  */
  2148.   if (buf[offset] != 0x48)
  2149.     offset--;

  2151.   if (buf[offset + 2] != 0xe4
  2152.       || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
  2153.     return pc;

  2155.   offset_and = offset;
  2156.   offset += buf[offset + 1] == 0x81 ? 7 : 4;

  2158.   /* Skip optional addr32 prefix.  */
  2159.   if (buf[offset] == 0x67)
  2160.     offset++;

  2162.   /* The next instruction has to be "pushq -8(%reg)".  */
  2163.   r = 0;
  2164.   if (buf[offset] == 0xff)
  2165.     offset++;
  2166.   else if ((buf[offset] & 0xf6) == 0x40
  2167.            && buf[offset + 1] == 0xff)
  2168.     {
  2169.       /* Check the REX.B bit.  */
  2170.       if ((buf[offset] & 0x1) != 0)
  2171.         r = 8;
  2172.       offset += 2;
  2173.     }
  2174.   else
  2175.     return pc;

  2177.   /* 8bit -8 is 0xf8.  REG must be binary 110 and MOD must be binary
  2178.      01.  */
  2179.   if (buf[offset + 1] != 0xf8
  2180.       || (buf[offset] & 0xf8) != 0x70)
  2181.     return pc;

  2183.   /* R/M has register.  */
  2184.   r += buf[offset] & 7;

  2186.   /* Registers in leaq and pushq have to be the same.  */
  2187.   if (reg != r)
  2188.     return pc;

  2190.   if (current_pc > pc + offset_and)
  2191.     cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);

  2193.   return min (pc + offset + 2, current_pc);
  2194. }

  2196. /* Do a limited analysis of the prologue at PC and update CACHE
  2197.    accordingly.  Bail out early if CURRENT_PC is reached.  Return the
  2198.    address where the analysis stopped.

  2200.    We will handle only functions beginning with:

  2202.       pushq %rbp        0x55
  2203.       movq %rsp, %rbp   0x48 0x89 0xe5 (or 0x48 0x8b 0xec)

  2205.    or (for the X32 ABI):

  2207.       pushq %rbp        0x55
  2208.       movl %esp, %ebp   0x89 0xe5 (or 0x8b 0xec)

  2210.    Any function that doesn't start with one of these sequences will be
  2211.    assumed to have no prologue and thus no valid frame pointer in
  2212.    %rbp.  */

  2214. static CORE_ADDR
  2215. ‌amd64_analyze_prologue (struct gdbarch *gdbarch,
  2216.                         CORE_ADDR pc, CORE_ADDR current_pc,
  2217.                         struct amd64_frame_cache *cache)
  2218. {
  2219.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  2220.   /* There are two variations of movq %rsp, %rbp.  */
  2221.   static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
  2222.   static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
  2223.   /* Ditto for movl %esp, %ebp.  */
  2224.   static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
  2225.   static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };

  2227.   gdb_byte buf[3];
  2228.   gdb_byte op;

  2230.   if (current_pc <= pc)
  2231.     return current_pc;

  2233.   if (gdbarch_ptr_bit (gdbarch) == 32)
  2234.     pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
  2235.   else
  2236.     pc = amd64_analyze_stack_align (pc, current_pc, cache);

  2238.   op = read_code_unsigned_integer (pc, 1, byte_order);

  2240.   if (op == 0x55)                /* pushq %rbp */
  2241.     {
  2242.       /* Take into account that we've executed the `pushq %rbp' that
  2243.          starts this instruction sequence.  */
  2244.       cache->saved_regs[AMD64_RBP_REGNUM] = 0;
  2245.       cache->sp_offset += 8;

  2247.       /* If that's all, return now.  */
  2248.       if (current_pc <= pc + 1)
  2249.         return current_pc;

  2251.       read_code (pc + 1, buf, 3);

  2253.       /* Check for `movq %rsp, %rbp'.  */
  2254.       if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
  2255.           || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
  2256.         {
  2257.           /* OK, we actually have a frame.  */
  2258.           cache->frameless_p = 0;
  2259.           return pc + 4;
  2260.         }

  2262.       /* For X32, also check for `movq %esp, %ebp'.  */
  2263.       if (gdbarch_ptr_bit (gdbarch) == 32)
  2264.         {
  2265.           if (memcmp (buf, mov_esp_ebp_1, 2) == 0
  2266.               || memcmp (buf, mov_esp_ebp_2, 2) == 0)
  2267.             {
  2268.               /* OK, we actually have a frame.  */
  2269.               cache->frameless_p = 0;
  2270.               return pc + 3;
  2271.             }
  2272.         }

  2274.       return pc + 1;
  2275.     }

  2277.   return pc;
  2278. }

  2280. /* Work around false termination of prologue - GCC PR debug/48827.

  2282.    START_PC is the first instruction of a function, PC is its minimal already
  2283.    determined advanced address.  Function returns PC if it has nothing to do.

  2285.    84 c0                test   %al,%al
  2286.    74 23                je     after
  2287.    <-- here is 0 lines advance - the false prologue end marker.
  2288.    0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
  2289.    0f 29 4d 80          movaps %xmm1,-0x80(%rbp)
  2290.    0f 29 55 90          movaps %xmm2,-0x70(%rbp)
  2291.    0f 29 5d a0          movaps %xmm3,-0x60(%rbp)
  2292.    0f 29 65 b0          movaps %xmm4,-0x50(%rbp)
  2293.    0f 29 6d c0          movaps %xmm5,-0x40(%rbp)
  2294.    0f 29 75 d0          movaps %xmm6,-0x30(%rbp)
  2295.    0f 29 7d e0          movaps %xmm7,-0x20(%rbp)
  2296.    after:  */

  2298. static CORE_ADDR
  2299. ‌amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
  2300. {
  2301.   struct symtab_and_line start_pc_sal, next_sal;
  2302.   gdb_byte buf[4 + 8 * 7];
  2303.   int offset, xmmreg;

  2305.   if (pc == start_pc)
  2306.     return pc;

  2308.   start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
  2309.   if (start_pc_sal.symtab == NULL
  2310.       || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
  2311.            (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
  2312.       || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
  2313.     return pc;

  2315.   next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
  2316.   if (next_sal.line != start_pc_sal.line)
  2317.     return pc;

  2319.   /* START_PC can be from overlayed memory, ignored here.  */
  2320.   if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
  2321.     return pc;

  2323.   /* test %al,%al */
  2324.   if (buf[0] != 0x84 || buf[1] != 0xc0)
  2325.     return pc;
  2326.   /* je AFTER */
  2327.   if (buf[2] != 0x74)
  2328.     return pc;

  2330.   offset = 4;
  2331.   for (xmmreg = 0; xmmreg < 8; xmmreg++)
  2332.     {
  2333.       /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
  2334.       if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
  2335.           || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
  2336.         return pc;

  2338.       /* 0b01?????? */
  2339.       if ((buf[offset + 2] & 0xc0) == 0x40)
  2340.         {
  2341.           /* 8-bit displacement.  */
  2342.           offset += 4;
  2343.         }
  2344.       /* 0b10?????? */
  2345.       else if ((buf[offset + 2] & 0xc0) == 0x80)
  2346.         {
  2347.           /* 32-bit displacement.  */
  2348.           offset += 7;
  2349.         }
  2350.       else
  2351.         return pc;
  2352.     }

  2354.   /* je AFTER */
  2355.   if (offset - 4 != buf[3])
  2356.     return pc;

  2358.   return next_sal.end;
  2359. }

  2361. /* Return PC of first real instruction.  */

  2363. static CORE_ADDR
  2364. ‌amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
  2365. {
  2366.   struct amd64_frame_cache cache;
  2367.   CORE_ADDR pc;
  2368.   CORE_ADDR func_addr;

  2370.   if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
  2371.     {
  2372.       CORE_ADDR post_prologue_pc
  2373.         = skip_prologue_using_sal (gdbarch, func_addr);
  2374.       struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);

  2376.       /* Clang always emits a line note before the prologue and another
  2377.          one after.  We trust clang to emit usable line notes.  */
  2378.       if (post_prologue_pc
  2379.           && (cust != NULL
  2380.               && COMPUNIT_PRODUCER (cust) != NULL
  2381.               && strncmp (COMPUNIT_PRODUCER (cust), "clang ",
  2382.                           sizeof ("clang ") - 1) == 0))
  2383.         return max (start_pc, post_prologue_pc);
  2384.     }

  2386.   amd64_init_frame_cache (&cache);
  2387.   pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
  2388.                                &cache);
  2389.   if (cache.frameless_p)
  2390.     return start_pc;

  2392.   return amd64_skip_xmm_prologue (pc, start_pc);
  2393. }


  2396. /* Normal frames.  */

  2398. static void
  2399. ‌amd64_frame_cache_1 (struct frame_info *this_frame,
  2400.                      struct amd64_frame_cache *cache)
  2401. {
  2402.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  2403.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  2404.   gdb_byte buf[8];
  2405.   int i;

  2407.   cache->pc = get_frame_func (this_frame);
  2408.   if (cache->pc != 0)
  2409.     amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
  2410.                             cache);

  2412.   if (cache->frameless_p)
  2413.     {
  2414.       /* We didn't find a valid frame.  If we're at the start of a
  2415.          function, or somewhere half-way its prologue, the function's
  2416.          frame probably hasn't been fully setup yet.  Try to
  2417.          reconstruct the base address for the stack frame by looking
  2418.          at the stack pointer.  For truly "frameless" functions this
  2419.          might work too.  */

  2421.       if (cache->saved_sp_reg != -1)
  2422.         {
  2423.           /* Stack pointer has been saved.  */
  2424.           get_frame_register (this_frame, cache->saved_sp_reg, buf);
  2425.           cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);

  2427.           /* We're halfway aligning the stack.  */
  2428.           cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
  2429.           cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;

  2431.           /* This will be added back below.  */
  2432.           cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
  2433.         }
  2434.       else
  2435.         {
  2436.           get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
  2437.           cache->base = extract_unsigned_integer (buf, 8, byte_order)
  2438.                         + cache->sp_offset;
  2439.         }
  2440.     }
  2441.   else
  2442.     {
  2443.       get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
  2444.       cache->base = extract_unsigned_integer (buf, 8, byte_order);
  2445.     }

  2447.   /* Now that we have the base address for the stack frame we can
  2448.      calculate the value of %rsp in the calling frame.  */
  2449.   cache->saved_sp = cache->base + 16;

  2451.   /* For normal frames, %rip is stored at 8(%rbp).  If we don't have a
  2452.      frame we find it at the same offset from the reconstructed base
  2453.      address.  If we're halfway aligning the stack, %rip is handled
  2454.      differently (see above).  */
  2455.   if (!cache->frameless_p || cache->saved_sp_reg == -1)
  2456.     cache->saved_regs[AMD64_RIP_REGNUM] = 8;

  2458.   /* Adjust all the saved registers such that they contain addresses
  2459.      instead of offsets.  */
  2460.   for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
  2461.     if (cache->saved_regs[i] != -1)
  2462.       cache->saved_regs[i] += cache->base;

  2464.   cache->base_p = 1;
  2465. }

  2467. static struct amd64_frame_cache *
  2468. ‌amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
  2469. {
  2470.   volatile struct gdb_exception ex;
  2471.   struct amd64_frame_cache *cache;

  2473.   if (*this_cache)
  2474.     return *this_cache;

  2476.   cache = amd64_alloc_frame_cache ();
  2477.   *this_cache = cache;

  2479.   TRY_CATCH (ex, RETURN_MASK_ERROR)
  2480.     {
  2481.       amd64_frame_cache_1 (this_frame, cache);
  2482.     }
  2483.   if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
  2484.     throw_exception (ex);

  2486.   return cache;
  2487. }

  2489. static enum unwind_stop_reason
  2490. ‌amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
  2491.                                 void **this_cache)
  2492. {
  2493.   struct amd64_frame_cache *cache =
  2494.     amd64_frame_cache (this_frame, this_cache);

  2496.   if (!cache->base_p)
  2497.     return UNWIND_UNAVAILABLE;

  2499.   /* This marks the outermost frame.  */
  2500.   if (cache->base == 0)
  2501.     return UNWIND_OUTERMOST;

  2503.   return UNWIND_NO_REASON;
  2504. }

  2506. static void
  2507. ‌amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
  2508.                      struct frame_id *this_id)
  2509. {
  2510.   struct amd64_frame_cache *cache =
  2511.     amd64_frame_cache (this_frame, this_cache);

  2513.   if (!cache->base_p)
  2514.     (*this_id) = frame_id_build_unavailable_stack (cache->pc);
  2515.   else if (cache->base == 0)
  2516.     {
  2517.       /* This marks the outermost frame.  */
  2518.       return;
  2519.     }
  2520.   else
  2521.     (*this_id) = frame_id_build (cache->base + 16, cache->pc);
  2522. }

  2524. static struct value *
  2525. ‌amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
  2526.                            int regnum)
  2527. {
  2528.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  2529.   struct amd64_frame_cache *cache =
  2530.     amd64_frame_cache (this_frame, this_cache);

  2532.   gdb_assert (regnum >= 0);

  2534.   if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
  2535.     return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);

  2537.   if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
  2538.     return frame_unwind_got_memory (this_frame, regnum,
  2539.                                     cache->saved_regs[regnum]);

  2541.   return frame_unwind_got_register (this_frame, regnum, regnum);
  2542. }

  2544. ‌static const struct frame_unwind amd64_frame_unwind =
  2545. {
  2546.   NORMAL_FRAME,
  2547.   amd64_frame_unwind_stop_reason,
  2548.   amd64_frame_this_id,
  2549.   amd64_frame_prev_register,
  2550.   NULL,
  2551.   default_frame_sniffer
  2552. };

  2554. /* Generate a bytecode expression to get the value of the saved PC.  */

  2556. static void
  2557. ‌amd64_gen_return_address (struct gdbarch *gdbarch,
  2558.                           struct agent_expr *ax, struct axs_value *value,
  2559.                           CORE_ADDR scope)
  2560. {
  2561.   /* The following sequence assumes the traditional use of the base
  2562.      register.  */
  2563.   ax_reg (ax, AMD64_RBP_REGNUM);
  2564.   ax_const_l (ax, 8);
  2565.   ax_simple (ax, aop_add);
  2566.   value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
  2567.   value->kind = axs_lvalue_memory;
  2568. }


  2571. /* Signal trampolines.  */

  2573. /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
  2574.    64-bit variants.  This would require using identical frame caches
  2575.    on both platforms.  */

  2577. static struct amd64_frame_cache *
  2578. ‌amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
  2579. {
  2580.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  2581.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  2582.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  2583.   volatile struct gdb_exception ex;
  2584.   struct amd64_frame_cache *cache;
  2585.   CORE_ADDR addr;
  2586.   gdb_byte buf[8];
  2587.   int i;

  2589.   if (*this_cache)
  2590.     return *this_cache;

  2592.   cache = amd64_alloc_frame_cache ();

  2594.   TRY_CATCH (ex, RETURN_MASK_ERROR)
  2595.     {
  2596.       get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
  2597.       cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;

  2599.       addr = tdep->sigcontext_addr (this_frame);
  2600.       gdb_assert (tdep->sc_reg_offset);
  2601.       gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
  2602.       for (i = 0; i < tdep->sc_num_regs; i++)
  2603.         if (tdep->sc_reg_offset[i] != -1)
  2604.           cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];

  2606.       cache->base_p = 1;
  2607.     }
  2608.   if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
  2609.     throw_exception (ex);

  2611.   *this_cache = cache;
  2612.   return cache;
  2613. }

  2615. static enum unwind_stop_reason
  2616. ‌amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
  2617.                                          void **this_cache)
  2618. {
  2619.   struct amd64_frame_cache *cache =
  2620.     amd64_sigtramp_frame_cache (this_frame, this_cache);

  2622.   if (!cache->base_p)
  2623.     return UNWIND_UNAVAILABLE;

  2625.   return UNWIND_NO_REASON;
  2626. }

  2628. static void
  2629. ‌amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
  2630.                               void **this_cache, struct frame_id *this_id)
  2631. {
  2632.   struct amd64_frame_cache *cache =
  2633.     amd64_sigtramp_frame_cache (this_frame, this_cache);

  2635.   if (!cache->base_p)
  2636.     (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
  2637.   else if (cache->base == 0)
  2638.     {
  2639.       /* This marks the outermost frame.  */
  2640.       return;
  2641.     }
  2642.   else
  2643.     (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
  2644. }

  2646. static struct value *
  2647. ‌amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
  2648.                                     void **this_cache, int regnum)
  2649. {
  2650.   /* Make sure we've initialized the cache.  */
  2651.   amd64_sigtramp_frame_cache (this_frame, this_cache);

  2653.   return amd64_frame_prev_register (this_frame, this_cache, regnum);
  2654. }

  2656. static int
  2657. ‌amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
  2658.                               struct frame_info *this_frame,
  2659.                               void **this_cache)
  2660. {
  2661.   struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));

  2663.   /* We shouldn't even bother if we don't have a sigcontext_addr
  2664.      handler.  */
  2665.   if (tdep->sigcontext_addr == NULL)
  2666.     return 0;

  2668.   if (tdep->sigtramp_p != NULL)
  2669.     {
  2670.       if (tdep->sigtramp_p (this_frame))
  2671.         return 1;
  2672.     }

  2674.   if (tdep->sigtramp_start != 0)
  2675.     {
  2676.       CORE_ADDR pc = get_frame_pc (this_frame);

  2678.       gdb_assert (tdep->sigtramp_end != 0);
  2679.       if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
  2680.         return 1;
  2681.     }

  2683.   return 0;
  2684. }

  2686. ‌static const struct frame_unwind amd64_sigtramp_frame_unwind =
  2687. {
  2688.   SIGTRAMP_FRAME,
  2689.   amd64_sigtramp_frame_unwind_stop_reason,
  2690.   amd64_sigtramp_frame_this_id,
  2691.   amd64_sigtramp_frame_prev_register,
  2692.   NULL,
  2693.   amd64_sigtramp_frame_sniffer
  2694. };


  2697. static CORE_ADDR
  2698. ‌amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
  2699. {
  2700.   struct amd64_frame_cache *cache =
  2701.     amd64_frame_cache (this_frame, this_cache);

  2703.   return cache->base;
  2704. }

  2706. ‌static const struct frame_base amd64_frame_base =
  2707. {
  2708.   &amd64_frame_unwind,
  2709.   amd64_frame_base_address,
  2710.   amd64_frame_base_address,
  2711.   amd64_frame_base_address
  2712. };

  2714. /* Normal frames, but in a function epilogue.  */

  2716. /* The epilogue is defined here as the 'ret' instruction, which will
  2717.    follow any instruction such as 'leave' or 'pop %ebp' that destroys
  2718.    the function's stack frame.  */

  2720. static int
  2721. ‌amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
  2722. {
  2723.   gdb_byte insn;
  2724.   struct compunit_symtab *cust;

  2726.   cust = find_pc_compunit_symtab (pc);
  2727.   if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
  2728.     return 0;

  2730.   if (target_read_memory (pc, &insn, 1))
  2731.     return 0;   /* Can't read memory at pc.  */

  2733.   if (insn != 0xc3)     /* 'ret' instruction.  */
  2734.     return 0;

  2736.   return 1;
  2737. }

  2739. static int
  2740. ‌amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
  2741.                               struct frame_info *this_frame,
  2742.                               void **this_prologue_cache)
  2743. {
  2744.   if (frame_relative_level (this_frame) == 0)
  2745.     return amd64_in_function_epilogue_p (get_frame_arch (this_frame),
  2746.                                          get_frame_pc (this_frame));
  2747.   else
  2748.     return 0;
  2749. }

  2751. static struct amd64_frame_cache *
  2752. ‌amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
  2753. {
  2754.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  2755.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  2756.   volatile struct gdb_exception ex;
  2757.   struct amd64_frame_cache *cache;
  2758.   gdb_byte buf[8];

  2760.   if (*this_cache)
  2761.     return *this_cache;

  2763.   cache = amd64_alloc_frame_cache ();
  2764.   *this_cache = cache;

  2766.   TRY_CATCH (ex, RETURN_MASK_ERROR)
  2767.     {
  2768.       /* Cache base will be %esp plus cache->sp_offset (-8).  */
  2769.       get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
  2770.       cache->base = extract_unsigned_integer (buf, 8,
  2771.                                               byte_order) + cache->sp_offset;

  2773.       /* Cache pc will be the frame func.  */
  2774.       cache->pc = get_frame_pc (this_frame);

  2776.       /* The saved %esp will be at cache->base plus 16.  */
  2777.       cache->saved_sp = cache->base + 16;

  2779.       /* The saved %eip will be at cache->base plus 8.  */
  2780.       cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;

  2782.       cache->base_p = 1;
  2783.     }
  2784.   if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR)
  2785.     throw_exception (ex);

  2787.   return cache;
  2788. }

  2790. static enum unwind_stop_reason
  2791. ‌amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
  2792.                                          void **this_cache)
  2793. {
  2794.   struct amd64_frame_cache *cache
  2795.     = amd64_epilogue_frame_cache (this_frame, this_cache);

  2797.   if (!cache->base_p)
  2798.     return UNWIND_UNAVAILABLE;

  2800.   return UNWIND_NO_REASON;
  2801. }

  2803. static void
  2804. ‌amd64_epilogue_frame_this_id (struct frame_info *this_frame,
  2805.                               void **this_cache,
  2806.                               struct frame_id *this_id)
  2807. {
  2808.   struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
  2809.                                                                this_cache);

  2811.   if (!cache->base_p)
  2812.     (*this_id) = frame_id_build_unavailable_stack (cache->pc);
  2813.   else
  2814.     (*this_id) = frame_id_build (cache->base + 8, cache->pc);
  2815. }

  2817. ‌static const struct frame_unwind amd64_epilogue_frame_unwind =
  2818. {
  2819.   NORMAL_FRAME,
  2820.   amd64_epilogue_frame_unwind_stop_reason,
  2821.   amd64_epilogue_frame_this_id,
  2822.   amd64_frame_prev_register,
  2823.   NULL,
  2824.   amd64_epilogue_frame_sniffer
  2825. };

  2827. static struct frame_id
  2828. ‌amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
  2829. {
  2830.   CORE_ADDR fp;

  2832.   fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);

  2834.   return frame_id_build (fp + 16, get_frame_pc (this_frame));
  2835. }

  2837. /* 16 byte align the SP per frame requirements.  */

  2839. static CORE_ADDR
  2840. ‌amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  2841. {
  2842.   return sp & -(CORE_ADDR)16;
  2843. }


  2846. /* Supply register REGNUM from the buffer specified by FPREGS and LEN
  2847.    in the floating-point register set REGSET to register cache
  2848.    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

  2850. static void
  2851. ‌amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
  2852.                        int regnum, const void *fpregs, size_t len)
  2853. {
  2854.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  2855.   const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  2857.   gdb_assert (len == tdep->sizeof_fpregset);
  2858.   amd64_supply_fxsave (regcache, regnum, fpregs);
  2859. }

  2861. /* Collect register REGNUM from the register cache REGCACHE and store
  2862.    it in the buffer specified by FPREGS and LEN as described by the
  2863.    floating-point register set REGSET.  If REGNUM is -1, do this for
  2864.    all registers in REGSET.  */

  2866. static void
  2867. ‌amd64_collect_fpregset (const struct regset *regset,
  2868.                         const struct regcache *regcache,
  2869.                         int regnum, void *fpregs, size_t len)
  2870. {
  2871.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  2872.   const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  2874.   gdb_assert (len == tdep->sizeof_fpregset);
  2875.   amd64_collect_fxsave (regcache, regnum, fpregs);
  2876. }

  2878. ‌const struct regset amd64_fpregset =
  2879.   {
  2880.     NULL, amd64_supply_fpregset, amd64_collect_fpregset
  2881.   };


  2884. /* Figure out where the longjmp will land.  Slurp the jmp_buf out of
  2885.    %rdi.  We expect its value to be a pointer to the jmp_buf structure
  2886.    from which we extract the address that we will land at.  This
  2887.    address is copied into PC.  This routine returns non-zero on
  2888.    success.  */

  2890. static int
  2891. ‌amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
  2892. {
  2893.   gdb_byte buf[8];
  2894.   CORE_ADDR jb_addr;
  2895.   struct gdbarch *gdbarch = get_frame_arch (frame);
  2896.   int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
  2897.   int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);

  2899.   /* If JB_PC_OFFSET is -1, we have no way to find out where the
  2900.      longjmp will land.         */
  2901.   if (jb_pc_offset == -1)
  2902.     return 0;

  2904.   get_frame_register (frame, AMD64_RDI_REGNUM, buf);
  2905.   jb_addr= extract_typed_address
  2906.             (buf, builtin_type (gdbarch)->builtin_data_ptr);
  2907.   if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
  2908.     return 0;

  2910.   *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);

  2912.   return 1;
  2913. }

  2915. ‌static const int amd64_record_regmap[] =
  2916. {
  2917.   AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
  2918.   AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
  2919.   AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
  2920.   AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
  2921.   AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
  2922.   AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
  2923. };

  2925. void
  2926. ‌amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
  2927. {
  2928.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  2929.   const struct target_desc *tdesc = info.target_desc;
  2930.   static const char *const stap_integer_prefixes[] = { "$", NULL };
  2931.   static const char *const stap_register_prefixes[] = { "%", NULL };
  2932.   static const char *const stap_register_indirection_prefixes[] = { "(",
  2933.                                                                     NULL };
  2934.   static const char *const stap_register_indirection_suffixes[] = { ")",
  2935.                                                                     NULL };

  2937.   /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
  2938.      floating-point registers.  */
  2939.   tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
  2940.   tdep->fpregset = &amd64_fpregset;

  2942.   if (! tdesc_has_registers (tdesc))
  2943.     tdesc = tdesc_amd64;
  2944.   tdep->tdesc = tdesc;

  2946.   tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
  2947.   tdep->register_names = amd64_register_names;

  2949.   if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
  2950.     {
  2951.       tdep->zmmh_register_names = amd64_zmmh_names;
  2952.       tdep->k_register_names = amd64_k_names;
  2953.       tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
  2954.       tdep->ymm16h_register_names = amd64_ymmh_avx512_names;

  2956.       tdep->num_zmm_regs = 32;
  2957.       tdep->num_xmm_avx512_regs = 16;
  2958.       tdep->num_ymm_avx512_regs = 16;

  2960.       tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
  2961.       tdep->k0_regnum = AMD64_K0_REGNUM;
  2962.       tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
  2963.       tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
  2964.     }

  2966.   if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
  2967.     {
  2968.       tdep->ymmh_register_names = amd64_ymmh_names;
  2969.       tdep->num_ymm_regs = 16;
  2970.       tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
  2971.     }

  2973.   if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
  2974.     {
  2975.       tdep->mpx_register_names = amd64_mpx_names;
  2976.       tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
  2977.       tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
  2978.     }

  2980.   tdep->num_byte_regs = 20;
  2981.   tdep->num_word_regs = 16;
  2982.   tdep->num_dword_regs = 16;
  2983.   /* Avoid wiring in the MMX registers for now.  */
  2984.   tdep->num_mmx_regs = 0;

  2986.   set_gdbarch_pseudo_register_read_value (gdbarch,
  2987.                                           amd64_pseudo_register_read_value);
  2988.   set_gdbarch_pseudo_register_write (gdbarch,
  2989.                                      amd64_pseudo_register_write);

  2991.   set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);

  2993.   /* AMD64 has an FPU and 16 SSE registers.  */
  2994.   tdep->st0_regnum = AMD64_ST0_REGNUM;
  2995.   tdep->num_xmm_regs = 16;

  2997.   /* This is what all the fuss is about.  */
  2998.   set_gdbarch_long_bit (gdbarch, 64);
  2999.   set_gdbarch_long_long_bit (gdbarch, 64);
  3000.   set_gdbarch_ptr_bit (gdbarch, 64);

  3002.   /* In contrast to the i386, on AMD64 a `long double' actually takes
  3003.      up 128 bits, even though it's still based on the i387 extended
  3004.      floating-point format which has only 80 significant bits.  */
  3005.   set_gdbarch_long_double_bit (gdbarch, 128);

  3007.   set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);

  3009.   /* Register numbers of various important registers.  */
  3010.   set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
  3011.   set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
  3012.   set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
  3013.   set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */

  3015.   /* The "default" register numbering scheme for AMD64 is referred to
  3016.      as the "DWARF Register Number Mapping" in the System V psABI.
  3017.      The preferred debugging format for all known AMD64 targets is
  3018.      actually DWARF2, and GCC doesn't seem to support DWARF (that is
  3019.      DWARF-1), but we provide the same mapping just in case.  This
  3020.      mapping is also used for stabs, which GCC does support.  */
  3021.   set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
  3022.   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);

  3024.   /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
  3025.      be in use on any of the supported AMD64 targets.  */

  3027.   /* Call dummy code.  */
  3028.   set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
  3029.   set_gdbarch_frame_align (gdbarch, amd64_frame_align);
  3030.   set_gdbarch_frame_red_zone_size (gdbarch, 128);

  3032.   set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
  3033.   set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
  3034.   set_gdbarch_value_to_register (gdbarch, i387_value_to_register);

  3036.   set_gdbarch_return_value (gdbarch, amd64_return_value);

  3038.   set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);

  3040.   tdep->record_regmap = amd64_record_regmap;

  3042.   set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);

  3044.   /* Hook the function epilogue frame unwinder.  This unwinder is
  3045.      appended to the list first, so that it supercedes the other
  3046.      unwinders in function epilogues.  */
  3047.   frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);

  3049.   /* Hook the prologue-based frame unwinders.  */
  3050.   frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
  3051.   frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
  3052.   frame_base_set_default (gdbarch, &amd64_frame_base);

  3054.   set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);

  3056.   set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);

  3058.   set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);

  3060.   /* SystemTap variables and functions.  */
  3061.   set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
  3062.   set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
  3063.   set_gdbarch_stap_register_indirection_prefixes (gdbarch,
  3064.                                           stap_register_indirection_prefixes);
  3065.   set_gdbarch_stap_register_indirection_suffixes (gdbarch,
  3066.                                           stap_register_indirection_suffixes);
  3067.   set_gdbarch_stap_is_single_operand (gdbarch,
  3068.                                       i386_stap_is_single_operand);
  3069.   set_gdbarch_stap_parse_special_token (gdbarch,
  3070.                                         i386_stap_parse_special_token);
  3071.   set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
  3072.   set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
  3073.   set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
  3074. }


  3077. static struct type *
  3078. ‌amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
  3079. {
  3080.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  3082.   switch (regnum - tdep->eax_regnum)
  3083.     {
  3084.     case AMD64_RBP_REGNUM:        /* %ebp */
  3085.     case AMD64_RSP_REGNUM:        /* %esp */
  3086.       return builtin_type (gdbarch)->builtin_data_ptr;
  3087.     case AMD64_RIP_REGNUM:        /* %eip */
  3088.       return builtin_type (gdbarch)->builtin_func_ptr;
  3089.     }

  3091.   return i386_pseudo_register_type (gdbarch, regnum);
  3092. }

  3094. void
  3095. ‌amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
  3096. {
  3097.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  3098.   const struct target_desc *tdesc = info.target_desc;

  3100.   amd64_init_abi (info, gdbarch);

  3102.   if (! tdesc_has_registers (tdesc))
  3103.     tdesc = tdesc_x32;
  3104.   tdep->tdesc = tdesc;

  3106.   tdep->num_dword_regs = 17;
  3107.   set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);

  3109.   set_gdbarch_long_bit (gdbarch, 32);
  3110.   set_gdbarch_ptr_bit (gdbarch, 32);
  3111. }

  3113. /* Provide a prototype to silence -Wmissing-prototypes.  */
  3114. void _initialize_amd64_tdep (void);

  3116. void
  3117. ‌_initialize_amd64_tdep (void)
  3118. {
  3119.   initialize_tdesc_amd64 ();
  3120.   initialize_tdesc_amd64_avx ();
  3121.   initialize_tdesc_amd64_mpx ();
  3122.   initialize_tdesc_amd64_avx512 ();

  3124.   initialize_tdesc_x32 ();
  3125.   initialize_tdesc_x32_avx ();
  3126.   initialize_tdesc_x32_avx512 ();
  3127. }


  3130. /* The 64-bit FXSAVE format differs from the 32-bit format in the
  3131.    sense that the instruction pointer and data pointer are simply
  3132.    64-bit offsets into the code segment and the data segment instead
  3133.    of a selector offset pair.  The functions below store the upper 32
  3134.    bits of these pointers (instead of just the 16-bits of the segment
  3135.    selector).  */

  3137. /* Fill register REGNUM in REGCACHE with the appropriate
  3138.    floating-point or SSE register value from *FXSAVE.  If REGNUM is
  3139.    -1, do this for all registers.  This function masks off any of the
  3140.    reserved bits in *FXSAVE.  */

  3142. void
  3143. ‌amd64_supply_fxsave (struct regcache *regcache, int regnum,
  3144.                      const void *fxsave)
  3145. {
  3146.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  3147.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  3149.   i387_supply_fxsave (regcache, regnum, fxsave);

  3151.   if (fxsave
  3152.       && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
  3153.     {
  3154.       const gdb_byte *regs = fxsave;

  3156.       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
  3157.         regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
  3158.       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
  3159.         regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
  3160.     }
  3161. }

  3163. /* Similar to amd64_supply_fxsave, but use XSAVE extended state.  */

  3165. void
  3166. ‌amd64_supply_xsave (struct regcache *regcache, int regnum,
  3167.                     const void *xsave)
  3168. {
  3169.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  3170.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  3172.   i387_supply_xsave (regcache, regnum, xsave);

  3174.   if (xsave
  3175.       && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
  3176.     {
  3177.       const gdb_byte *regs = xsave;

  3179.       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
  3180.         regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
  3181.                              regs + 12);
  3182.       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
  3183.         regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
  3184.                              regs + 20);
  3185.     }
  3186. }

  3188. /* Fill register REGNUM (if it is a floating-point or SSE register) in
  3189.    *FXSAVE with the value from REGCACHE.  If REGNUM is -1, do this for
  3190.    all registers.  This function doesn't touch any of the reserved
  3191.    bits in *FXSAVE.  */

  3193. void
  3194. ‌amd64_collect_fxsave (const struct regcache *regcache, int regnum,
  3195.                       void *fxsave)
  3196. {
  3197.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  3198.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  3199.   gdb_byte *regs = fxsave;

  3201.   i387_collect_fxsave (regcache, regnum, fxsave);

  3203.   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
  3204.     {
  3205.       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
  3206.         regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
  3207.       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
  3208.         regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
  3209.     }
  3210. }

  3212. /* Similar to amd64_collect_fxsave, but use XSAVE extended state.  */

  3214. void
  3215. ‌amd64_collect_xsave (const struct regcache *regcache, int regnum,
  3216.                      void *xsave, int gcore)
  3217. {
  3218.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  3219.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  3220.   gdb_byte *regs = xsave;

  3222.   i387_collect_xsave (regcache, regnum, xsave, gcore);

  3224.   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
  3225.     {
  3226.       if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
  3227.         regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
  3228.                               regs + 12);
  3229.       if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
  3230.         regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
  3231.                               regs + 20);
  3232.     }
  3233. }