gdb/sh-tdep.c - gdb

Global variables defined

Data types defined

Functions defined

Macros defined

Source code

  1. /* Target-dependent code for Renesas Super-H, for GDB.

  3.    Copyright (C) 1993-2015 Free Software Foundation, Inc.

  5.    This file is part of GDB.

  7.    This program is free software; you can redistribute it and/or modify
  8.    it under the terms of the GNU General Public License as published by
  9.    the Free Software Foundation; either version 3 of the License, or
  10.    (at your option) any later version.

  12.    This program is distributed in the hope that it will be useful,
  13.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.    GNU General Public License for more details.

  17.    You should have received a copy of the GNU General Public License
  18.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  20. /* Contributed by Steve Chamberlain
  21.    sac@cygnus.com.  */

  23. #include "defs.h"
  24. #include "frame.h"
  25. #include "frame-base.h"
  26. #include "frame-unwind.h"
  27. #include "dwarf2-frame.h"
  28. #include "symtab.h"
  29. #include "gdbtypes.h"
  30. #include "gdbcmd.h"
  31. #include "gdbcore.h"
  32. #include "value.h"
  33. #include "dis-asm.h"
  34. #include "inferior.h"
  35. #include "arch-utils.h"
  36. #include "floatformat.h"
  37. #include "regcache.h"
  38. #include "doublest.h"
  39. #include "osabi.h"
  40. #include "reggroups.h"
  41. #include "regset.h"
  42. #include "objfiles.h"

  44. #include "sh-tdep.h"
  45. #include "sh64-tdep.h"

  47. #include "elf-bfd.h"
  48. #include "solib-svr4.h"

  50. /* sh flags */
  51. #include "elf/sh.h"
  52. #include "dwarf2.h"
  53. /* registers numbers shared with the simulator.  */
  54. #include "gdb/sim-sh.h"

  56. /* List of "set sh ..." and "show sh ..." commands.  */
  57. ‌static struct cmd_list_element *setshcmdlist = NULL;
  58. ‌static struct cmd_list_element *showshcmdlist = NULL;

  60. ‌static const char sh_cc_gcc[] = "gcc";
  61. ‌static const char sh_cc_renesas[] = "renesas";
  62. ‌static const char *const sh_cc_enum[] = {
  63.   sh_cc_gcc,
  64.   sh_cc_renesas,
  65.   NULL
  66. };

  68. ‌static const char *sh_active_calling_convention = sh_cc_gcc;

  70. ‌#define SH_NUM_REGS 67

  72. ‌struct sh_frame_cache
  73. {
  74.   /* Base address.  */
  75.   CORE_ADDR base;
  76.   LONGEST sp_offset;
  77.   CORE_ADDR pc;

  79.   /* Flag showing that a frame has been created in the prologue code.  */
  80.   int uses_fp;

  82.   /* Saved registers.  */
  83.   CORE_ADDR saved_regs[SH_NUM_REGS];
  84.   CORE_ADDR saved_sp;
  85. };

  87. static int
  88. ‌sh_is_renesas_calling_convention (struct type *func_type)
  89. {
  90.   int val = 0;

  92.   if (func_type)
  93.     {
  94.       func_type = check_typedef (func_type);

  96.       if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
  97.         func_type = check_typedef (TYPE_TARGET_TYPE (func_type));

  99.       if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
  100.           && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
  101.         val = 1;
  102.     }

  104.   if (sh_active_calling_convention == sh_cc_renesas)
  105.     val = 1;

  107.   return val;
  108. }

  110. static const char *
  111. ‌sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
  112. {
  113.   static char *register_names[] = {
  114.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  115.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  116.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  117.     "", "",
  118.     "", "", "", "", "", "", "", "",
  119.     "", "", "", "", "", "", "", "",
  120.     "", "",
  121.     "", "", "", "", "", "", "", "",
  122.     "", "", "", "", "", "", "", "",
  123.     "", "", "", "", "", "", "", "",
  124.   };
  125.   if (reg_nr < 0)
  126.     return NULL;
  127.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  128.     return NULL;
  129.   return register_names[reg_nr];
  130. }

  132. static const char *
  133. ‌sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
  134. {
  135.   static char *register_names[] = {
  136.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  137.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  138.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  139.     "", "",
  140.     "", "", "", "", "", "", "", "",
  141.     "", "", "", "", "", "", "", "",
  142.     "ssr", "spc",
  143.     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  144.     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
  145.     "", "", "", "", "", "", "", "",
  146.   };
  147.   if (reg_nr < 0)
  148.     return NULL;
  149.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  150.     return NULL;
  151.   return register_names[reg_nr];
  152. }

  154. static const char *
  155. ‌sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
  156. {
  157.   static char *register_names[] = {
  158.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  159.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  160.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  161.     "fpul", "fpscr",
  162.     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
  163.     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  164.     "ssr", "spc",
  165.     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  166.     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  167.     "", "", "", "", "", "", "", "",
  168.   };
  169.   if (reg_nr < 0)
  170.     return NULL;
  171.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  172.     return NULL;
  173.   return register_names[reg_nr];
  174. }

  176. static const char *
  177. ‌sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
  178. {
  179.   static char *register_names[] = {
  180.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  181.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  182.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  183.     "fpul", "fpscr",
  184.     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
  185.     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  186.     "", "",
  187.     "", "", "", "", "", "", "", "",
  188.     "", "", "", "", "", "", "", "",
  189.     "", "", "", "", "", "", "", "",
  190.   };
  191.   if (reg_nr < 0)
  192.     return NULL;
  193.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  194.     return NULL;
  195.   return register_names[reg_nr];
  196. }

  198. static const char *
  199. ‌sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
  200. {
  201.   static char *register_names[] = {
  202.     /* general registers 0-15 */
  203.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  204.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  205.     /* 16 - 22 */
  206.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  207.     /* 23, 24 */
  208.     "fpul", "fpscr",
  209.     /* floating point registers 25 - 40 */
  210.     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
  211.     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  212.     /* 41, 42 */
  213.     "", "",
  214.     /* 43 - 62.  Banked registers.  The bank number used is determined by
  215.        the bank register (63).  */
  216.     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
  217.     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
  218.     "machb", "ivnb", "prb", "gbrb", "maclb",
  219.     /* 63: register bank number, not a real register but used to
  220.        communicate the register bank currently get/set.  This register
  221.        is hidden to the user, who manipulates it using the pseudo
  222.        register called "bank" (67).  See below.  */
  223.     "",
  224.     /* 64 - 66 */
  225.     "ibcr", "ibnr", "tbr",
  226.     /* 67: register bank number, the user visible pseudo register.  */
  227.     "bank",
  228.     /* double precision (pseudo) 68 - 75 */
  229.     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
  230.   };
  231.   if (reg_nr < 0)
  232.     return NULL;
  233.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  234.     return NULL;
  235.   return register_names[reg_nr];
  236. }

  238. static const char *
  239. ‌sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
  240. {
  241.   static char *register_names[] = {
  242.     /* general registers 0-15 */
  243.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  244.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  245.     /* 16 - 22 */
  246.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  247.     /* 23, 24 */
  248.     "", "",
  249.     /* floating point registers 25 - 40 */
  250.     "", "", "", "", "", "", "", "",
  251.     "", "", "", "", "", "", "", "",
  252.     /* 41, 42 */
  253.     "", "",
  254.     /* 43 - 62.  Banked registers.  The bank number used is determined by
  255.        the bank register (63).  */
  256.     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
  257.     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
  258.     "machb", "ivnb", "prb", "gbrb", "maclb",
  259.     /* 63: register bank number, not a real register but used to
  260.        communicate the register bank currently get/set.  This register
  261.        is hidden to the user, who manipulates it using the pseudo
  262.        register called "bank" (67).  See below.  */
  263.     "",
  264.     /* 64 - 66 */
  265.     "ibcr", "ibnr", "tbr",
  266.     /* 67: register bank number, the user visible pseudo register.  */
  267.     "bank",
  268.     /* double precision (pseudo) 68 - 75 */
  269.     "", "", "", "", "", "", "", "",
  270.   };
  271.   if (reg_nr < 0)
  272.     return NULL;
  273.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  274.     return NULL;
  275.   return register_names[reg_nr];
  276. }

  278. static const char *
  279. ‌sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
  280. {
  281.   static char *register_names[] = {
  282.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  283.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  284.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  285.     "", "dsr",
  286.     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
  287.     "y0", "y1", "", "", "", "", "", "mod",
  288.     "", "",
  289.     "rs", "re", "", "", "", "", "", "",
  290.     "", "", "", "", "", "", "", "",
  291.     "", "", "", "", "", "", "", "",
  292.   };
  293.   if (reg_nr < 0)
  294.     return NULL;
  295.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  296.     return NULL;
  297.   return register_names[reg_nr];
  298. }

  300. static const char *
  301. ‌sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
  302. {
  303.   static char *register_names[] = {
  304.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  305.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  306.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  307.     "", "dsr",
  308.     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
  309.     "y0", "y1", "", "", "", "", "", "mod",
  310.     "ssr", "spc",
  311.     "rs", "re", "", "", "", "", "", "",
  312.     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
  313.     "", "", "", "", "", "", "", "",
  314.     "", "", "", "", "", "", "", "",
  315.   };
  316.   if (reg_nr < 0)
  317.     return NULL;
  318.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  319.     return NULL;
  320.   return register_names[reg_nr];
  321. }

  323. static const char *
  324. ‌sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
  325. {
  326.   static char *register_names[] = {
  327.     /* general registers 0-15 */
  328.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  329.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  330.     /* 16 - 22 */
  331.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  332.     /* 23, 24 */
  333.     "fpul", "fpscr",
  334.     /* floating point registers 25 - 40 */
  335.     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
  336.     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  337.     /* 41, 42 */
  338.     "ssr", "spc",
  339.     /* bank 0 43 - 50 */
  340.     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  341.     /* bank 1 51 - 58 */
  342.     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  343.     /* 59 - 66 */
  344.     "", "", "", "", "", "", "", "",
  345.     /* pseudo bank register.  */
  346.     "",
  347.     /* double precision (pseudo) 68 - 75 */
  348.     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
  349.     /* vectors (pseudo) 76 - 79 */
  350.     "fv0", "fv4", "fv8", "fv12",
  351.     /* FIXME: missing XF */
  352.     /* FIXME: missing XD */
  353.   };
  354.   if (reg_nr < 0)
  355.     return NULL;
  356.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  357.     return NULL;
  358.   return register_names[reg_nr];
  359. }

  361. static const char *
  362. ‌sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
  363. {
  364.   static char *register_names[] = {
  365.     /* general registers 0-15 */
  366.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  367.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  368.     /* 16 - 22 */
  369.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  370.     /* 23, 24 */
  371.     "", "",
  372.     /* floating point registers 25 - 40 -- not for nofpu target */
  373.     "", "", "", "", "", "", "", "",
  374.     "", "", "", "", "", "", "", "",
  375.     /* 41, 42 */
  376.     "ssr", "spc",
  377.     /* bank 0 43 - 50 */
  378.     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  379.     /* bank 1 51 - 58 */
  380.     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  381.     /* 59 - 66 */
  382.     "", "", "", "", "", "", "", "",
  383.     /* pseudo bank register.  */
  384.     "",
  385.     /* double precision (pseudo) 68 - 75 -- not for nofpu target */
  386.     "", "", "", "", "", "", "", "",
  387.     /* vectors (pseudo) 76 - 79 -- not for nofpu target */
  388.     "", "", "", "",
  389.   };
  390.   if (reg_nr < 0)
  391.     return NULL;
  392.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  393.     return NULL;
  394.   return register_names[reg_nr];
  395. }

  397. static const char *
  398. ‌sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
  399. {
  400.   static char *register_names[] = {
  401.     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  402.     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  403.     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  404.     "", "dsr",
  405.     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
  406.     "y0", "y1", "", "", "", "", "", "mod",
  407.     "ssr", "spc",
  408.     "rs", "re", "", "", "", "", "", "",
  409.     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
  410.     "", "", "", "", "", "", "", "",
  411.     "", "", "", "", "", "", "", "",
  412.   };
  413.   if (reg_nr < 0)
  414.     return NULL;
  415.   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  416.     return NULL;
  417.   return register_names[reg_nr];
  418. }

  420. static const unsigned char *
  421. ‌sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
  422. {
  423.   /* 0xc3c3 is trapa #c3, and it works in big and little endian modes.  */
  424.   static unsigned char breakpoint[] = { 0xc3, 0xc3 };

  426.   /* For remote stub targets, trapa #20 is used.  */
  427.   if (strcmp (target_shortname, "remote") == 0)
  428.     {
  429.       static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
  430.       static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };

  432.       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
  433.         {
  434.           *lenptr = sizeof (big_remote_breakpoint);
  435.           return big_remote_breakpoint;
  436.         }
  437.       else
  438.         {
  439.           *lenptr = sizeof (little_remote_breakpoint);
  440.           return little_remote_breakpoint;
  441.         }
  442.     }

  444.   *lenptr = sizeof (breakpoint);
  445.   return breakpoint;
  446. }

  448. /* Prologue looks like
  449.    mov.l        r14,@-r15
  450.    sts.l        pr,@-r15
  451.    mov.l        <regs>,@-r15
  452.    sub                <room_for_loca_vars>,r15
  453.    mov                r15,r14

  455.    Actually it can be more complicated than this but that's it, basically.  */

  457. ‌#define GET_SOURCE_REG(x)          (((x) >> 4) & 0xf)
  458. ‌#define GET_TARGET_REG(x)          (((x) >> 8) & 0xf)

  460. /* JSR @Rm         0100mmmm00001011 */
  461. ‌#define IS_JSR(x)                (((x) & 0xf0ff) == 0x400b)

  463. /* STS.L PR,@-r15  0100111100100010
  464.    r15-4-->r15, PR-->(r15) */
  465. ‌#define IS_STS(x)                  ((x) == 0x4f22)

  467. /* STS.L MACL,@-r15  0100111100010010
  468.    r15-4-->r15, MACL-->(r15) */
  469. ‌#define IS_MACL_STS(x)          ((x) == 0x4f12)

  471. /* MOV.L Rm,@-r15  00101111mmmm0110
  472.    r15-4-->r15, Rm-->(R15) */
  473. ‌#define IS_PUSH(x)                 (((x) & 0xff0f) == 0x2f06)

  475. /* MOV r15,r14     0110111011110011
  476.    r15-->r14  */
  477. ‌#define IS_MOV_SP_FP(x)          ((x) == 0x6ef3)

  479. /* ADD #imm,r15    01111111iiiiiiii
  480.    r15+imm-->r15 */
  481. ‌#define IS_ADD_IMM_SP(x)         (((x) & 0xff00) == 0x7f00)

  483. ‌#define IS_MOV_R3(x)                 (((x) & 0xff00) == 0x1a00)
  484. ‌#define IS_SHLL_R3(x)                ((x) == 0x4300)

  486. /* ADD r3,r15      0011111100111100
  487.    r15+r3-->r15 */
  488. ‌#define IS_ADD_R3SP(x)                ((x) == 0x3f3c)

  490. /* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
  491.    FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
  492.    FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
  493. /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
  494.                    make this entirely clear.  */
  495. /* #define IS_FMOV(x)                (((x) & 0xf00f) == 0xf00b) */
  496. ‌#define IS_FPUSH(x)                (((x) & 0xff0f) == 0xff0b)

  498. /* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
  499. ‌#define IS_MOV_ARG_TO_REG(x) \
  500.         (((x) & 0xf00f) == 0x6003 && \
  501.          ((x) & 0x00f0) >= 0x0040 && \
  502.          ((x) & 0x00f0) <= 0x0070)
  503. /* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
  504. ‌#define IS_MOV_ARG_TO_IND_R14(x) \
  505.         (((x) & 0xff0f) == 0x2e02 && \
  506.          ((x) & 0x00f0) >= 0x0040 && \
  507.          ((x) & 0x00f0) <= 0x0070)
  508. /* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
  509. ‌#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
  510.         (((x) & 0xff00) == 0x1e00 && \
  511.          ((x) & 0x00f0) >= 0x0040 && \
  512.          ((x) & 0x00f0) <= 0x0070)

  514. /* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
  515. ‌#define IS_MOVW_PCREL_TO_REG(x)        (((x) & 0xf000) == 0x9000)
  516. /* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
  517. ‌#define IS_MOVL_PCREL_TO_REG(x)        (((x) & 0xf000) == 0xd000)
  518. /* MOVI20 #imm20,Rn           0000nnnniiii0000 */
  519. ‌#define IS_MOVI20(x)                (((x) & 0xf00f) == 0x0000)
  520. /* SUB Rn,R15                 00111111nnnn1000 */
  521. ‌#define IS_SUB_REG_FROM_SP(x)        (((x) & 0xff0f) == 0x3f08)

  523. ‌#define FPSCR_SZ                (1 << 20)

  525. /* The following instructions are used for epilogue testing.  */
  526. ‌#define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
  527. ‌#define IS_RTS(x)                ((x) == 0x000b)
  528. ‌#define IS_LDS(x)                  ((x) == 0x4f26)
  529. ‌#define IS_MACL_LDS(x)          ((x) == 0x4f16)
  530. ‌#define IS_MOV_FP_SP(x)          ((x) == 0x6fe3)
  531. ‌#define IS_ADD_REG_TO_FP(x)        (((x) & 0xff0f) == 0x3e0c)
  532. ‌#define IS_ADD_IMM_FP(x)         (((x) & 0xff00) == 0x7e00)

  534. static CORE_ADDR
  535. ‌sh_analyze_prologue (struct gdbarch *gdbarch,
  536.                      CORE_ADDR pc, CORE_ADDR limit_pc,
  537.                      struct sh_frame_cache *cache, ULONGEST fpscr)
  538. {
  539.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  540.   ULONGEST inst;
  541.   int offset;
  542.   int sav_offset = 0;
  543.   int r3_val = 0;
  544.   int reg, sav_reg = -1;

  546.   cache->uses_fp = 0;
  547.   for (; pc < limit_pc; pc += 2)
  548.     {
  549.       inst = read_memory_unsigned_integer (pc, 2, byte_order);
  550.       /* See where the registers will be saved to.  */
  551.       if (IS_PUSH (inst))
  552.         {
  553.           cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
  554.           cache->sp_offset += 4;
  555.         }
  556.       else if (IS_STS (inst))
  557.         {
  558.           cache->saved_regs[PR_REGNUM] = cache->sp_offset;
  559.           cache->sp_offset += 4;
  560.         }
  561.       else if (IS_MACL_STS (inst))
  562.         {
  563.           cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
  564.           cache->sp_offset += 4;
  565.         }
  566.       else if (IS_MOV_R3 (inst))
  567.         {
  568.           r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
  569.         }
  570.       else if (IS_SHLL_R3 (inst))
  571.         {
  572.           r3_val <<= 1;
  573.         }
  574.       else if (IS_ADD_R3SP (inst))
  575.         {
  576.           cache->sp_offset += -r3_val;
  577.         }
  578.       else if (IS_ADD_IMM_SP (inst))
  579.         {
  580.           offset = ((inst & 0xff) ^ 0x80) - 0x80;
  581.           cache->sp_offset -= offset;
  582.         }
  583.       else if (IS_MOVW_PCREL_TO_REG (inst))
  584.         {
  585.           if (sav_reg < 0)
  586.             {
  587.               reg = GET_TARGET_REG (inst);
  588.               if (reg < 14)
  589.                 {
  590.                   sav_reg = reg;
  591.                   offset = (inst & 0xff) << 1;
  592.                   sav_offset =
  593.                     read_memory_integer ((pc + 4) + offset, 2, byte_order);
  594.                 }
  595.             }
  596.         }
  597.       else if (IS_MOVL_PCREL_TO_REG (inst))
  598.         {
  599.           if (sav_reg < 0)
  600.             {
  601.               reg = GET_TARGET_REG (inst);
  602.               if (reg < 14)
  603.                 {
  604.                   sav_reg = reg;
  605.                   offset = (inst & 0xff) << 2;
  606.                   sav_offset =
  607.                     read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
  608.                                          4, byte_order);
  609.                 }
  610.             }
  611.         }
  612.       else if (IS_MOVI20 (inst)
  613.                && (pc + 2 < limit_pc))
  614.         {
  615.           if (sav_reg < 0)
  616.             {
  617.               reg = GET_TARGET_REG (inst);
  618.               if (reg < 14)
  619.                 {
  620.                   sav_reg = reg;
  621.                   sav_offset = GET_SOURCE_REG (inst) << 16;
  622.                   /* MOVI20 is a 32 bit instruction!  */
  623.                   pc += 2;
  624.                   sav_offset
  625.                     |= read_memory_unsigned_integer (pc, 2, byte_order);
  626.                   /* Now sav_offset contains an unsigned 20 bit value.
  627.                      It must still get sign extended.  */
  628.                   if (sav_offset & 0x00080000)
  629.                     sav_offset |= 0xfff00000;
  630.                 }
  631.             }
  632.         }
  633.       else if (IS_SUB_REG_FROM_SP (inst))
  634.         {
  635.           reg = GET_SOURCE_REG (inst);
  636.           if (sav_reg > 0 && reg == sav_reg)
  637.             {
  638.               sav_reg = -1;
  639.             }
  640.           cache->sp_offset += sav_offset;
  641.         }
  642.       else if (IS_FPUSH (inst))
  643.         {
  644.           if (fpscr & FPSCR_SZ)
  645.             {
  646.               cache->sp_offset += 8;
  647.             }
  648.           else
  649.             {
  650.               cache->sp_offset += 4;
  651.             }
  652.         }
  653.       else if (IS_MOV_SP_FP (inst))
  654.         {
  655.           pc += 2;
  656.           /* Don't go any further than six more instructions.  */
  657.           limit_pc = min (limit_pc, pc + (2 * 6));

  659.           cache->uses_fp = 1;
  660.           /* At this point, only allow argument register moves to other
  661.              registers or argument register moves to @(X,fp) which are
  662.              moving the register arguments onto the stack area allocated
  663.              by a former add somenumber to SP call.  Don't allow moving
  664.              to an fp indirect address above fp + cache->sp_offset.  */
  665.           for (; pc < limit_pc; pc += 2)
  666.             {
  667.               inst = read_memory_integer (pc, 2, byte_order);
  668.               if (IS_MOV_ARG_TO_IND_R14 (inst))
  669.                 {
  670.                   reg = GET_SOURCE_REG (inst);
  671.                   if (cache->sp_offset > 0)
  672.                     cache->saved_regs[reg] = cache->sp_offset;
  673.                 }
  674.               else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
  675.                 {
  676.                   reg = GET_SOURCE_REG (inst);
  677.                   offset = (inst & 0xf) * 4;
  678.                   if (cache->sp_offset > offset)
  679.                     cache->saved_regs[reg] = cache->sp_offset - offset;
  680.                 }
  681.               else if (IS_MOV_ARG_TO_REG (inst))
  682.                 continue;
  683.               else
  684.                 break;
  685.             }
  686.           break;
  687.         }
  688.       else if (IS_JSR (inst))
  689.         {
  690.           /* We have found a jsr that has been scheduled into the prologue.
  691.              If we continue the scan and return a pc someplace after this,
  692.              then setting a breakpoint on this function will cause it to
  693.              appear to be called after the function it is calling via the
  694.              jsr, which will be very confusing.  Most likely the next
  695.              instruction is going to be IS_MOV_SP_FP in the delay slot.  If
  696.              so, note that before returning the current pc.  */
  697.           if (pc + 2 < limit_pc)
  698.             {
  699.               inst = read_memory_integer (pc + 2, 2, byte_order);
  700.               if (IS_MOV_SP_FP (inst))
  701.                 cache->uses_fp = 1;
  702.             }
  703.           break;
  704.         }
  705. #if 0                /* This used to just stop when it found an instruction
  706.                    that was not considered part of the prologue.  Now,
  707.                    we just keep going looking for likely
  708.                    instructions.  */
  709.       else
  710.         break;
  711. #endif
  712.     }

  714.   return pc;
  715. }

  717. /* Skip any prologue before the guts of a function.  */
  718. static CORE_ADDR
  719. ‌sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  720. {
  721.   CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc;
  722.   struct sh_frame_cache cache;

  724.   /* See if we can determine the end of the prologue via the symbol table.
  725.      If so, then return either PC, or the PC after the prologue, whichever
  726.      is greater.  */
  727.   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
  728.     {
  729.       post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
  730.       if (post_prologue_pc != 0)
  731.         return max (pc, post_prologue_pc);
  732.     }

  734.   /* Can't determine prologue from the symbol table, need to examine
  735.      instructions.  */

  737.   /* Find an upper limit on the function prologue using the debug
  738.      information.  If the debug information could not be used to provide
  739.      that bound, then use an arbitrary large number as the upper bound.  */
  740.   limit_pc = skip_prologue_using_sal (gdbarch, pc);
  741.   if (limit_pc == 0)
  742.     /* Don't go any further than 28 instructions.  */
  743.     limit_pc = pc + (2 * 28);

  745.   /* Do not allow limit_pc to be past the function end, if we know
  746.      where that end is...  */
  747.   if (func_end_addr != 0)
  748.     limit_pc = min (limit_pc, func_end_addr);

  750.   cache.sp_offset = -4;
  751.   post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0);
  752.   if (cache.uses_fp)
  753.     pc = post_prologue_pc;

  755.   return pc;
  756. }

  758. /* The ABI says:

  760.    Aggregate types not bigger than 8 bytes that have the same size and
  761.    alignment as one of the integer scalar types are returned in the
  762.    same registers as the integer type they match.

  764.    For example, a 2-byte aligned structure with size 2 bytes has the
  765.    same size and alignment as a short int, and will be returned in R0.
  766.    A 4-byte aligned structure with size 8 bytes has the same size and
  767.    alignment as a long long int, and will be returned in R0 and R1.

  769.    When an aggregate type is returned in R0 and R1, R0 contains the
  770.    first four bytes of the aggregate, and R1 contains the
  771.    remainder.  If the size of the aggregate type is not a multiple of 4
  772.    bytes, the aggregate is tail-padded up to a multiple of 4
  773.    bytes.  The value of the padding is undefined.  For little-endian
  774.    targets the padding will appear at the most significant end of the
  775.    last element, for big-endian targets the padding appears at the
  776.    least significant end of the last element.

  778.    All other aggregate types are returned by address.  The caller
  779.    function passes the address of an area large enough to hold the
  780.    aggregate value in R2.  The called function stores the result in
  781.    this location.

  783.    To reiterate, structs smaller than 8 bytes could also be returned
  784.    in memory, if they don't pass the "same size and alignment as an
  785.    integer type" rule.

  787.    For example, in

  789.    struct s { char c[3]; } wibble;
  790.    struct s foo(void) {  return wibble; }

  792.    the return value from foo() will be in memory, not
  793.    in R0, because there is no 3-byte integer type.

  795.    Similarly, in

  797.    struct s { char c[2]; } wibble;
  798.    struct s foo(void) {  return wibble; }

  800.    because a struct containing two chars has alignment 1, that matches
  801.    type char, but size 2, that matches type short.  There's no integer
  802.    type that has alignment 1 and size 2, so the struct is returned in
  803.    memory.  */

  805. static int
  806. ‌sh_use_struct_convention (int renesas_abi, struct type *type)
  807. {
  808.   int len = TYPE_LENGTH (type);
  809.   int nelem = TYPE_NFIELDS (type);

  811.   /* The Renesas ABI returns aggregate types always on stack.  */
  812.   if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
  813.                       || TYPE_CODE (type) == TYPE_CODE_UNION))
  814.     return 1;

  816.   /* Non-power of 2 length types and types bigger than 8 bytes (which don't
  817.      fit in two registers anyway) use struct convention.  */
  818.   if (len != 1 && len != 2 && len != 4 && len != 8)
  819.     return 1;

  821.   /* Scalar types and aggregate types with exactly one field are aligned
  822.      by definition.  They are returned in registers.  */
  823.   if (nelem <= 1)
  824.     return 0;

  826.   /* If the first field in the aggregate has the same length as the entire
  827.      aggregate type, the type is returned in registers.  */
  828.   if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
  829.     return 0;

  831.   /* If the size of the aggregate is 8 bytes and the first field is
  832.      of size 4 bytes its alignment is equal to long long's alignment,
  833.      so it's returned in registers.  */
  834.   if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
  835.     return 0;

  837.   /* Otherwise use struct convention.  */
  838.   return 1;
  839. }

  841. static int
  842. ‌sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
  843. {
  844.   /* The Renesas ABI returns long longs/doubles etc. always on stack.  */
  845.   if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
  846.     return 1;
  847.   return sh_use_struct_convention (renesas_abi, type);
  848. }

  850. static CORE_ADDR
  851. ‌sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
  852. {
  853.   return sp & ~3;
  854. }

  856. /* Function: push_dummy_call (formerly push_arguments)
  857.    Setup the function arguments for calling a function in the inferior.

  859.    On the Renesas SH architecture, there are four registers (R4 to R7)
  860.    which are dedicated for passing function arguments.  Up to the first
  861.    four arguments (depending on size) may go into these registers.
  862.    The rest go on the stack.

  864.    MVS: Except on SH variants that have floating point registers.
  865.    In that case, float and double arguments are passed in the same
  866.    manner, but using FP registers instead of GP registers.

  868.    Arguments that are smaller than 4 bytes will still take up a whole
  869.    register or a whole 32-bit word on the stack, and will be
  870.    right-justified in the register or the stack word.  This includes
  871.    chars, shorts, and small aggregate types.

  873.    Arguments that are larger than 4 bytes may be split between two or
  874.    more registers.  If there are not enough registers free, an argument
  875.    may be passed partly in a register (or registers), and partly on the
  876.    stack.  This includes doubles, long longs, and larger aggregates.
  877.    As far as I know, there is no upper limit to the size of aggregates
  878.    that will be passed in this way; in other words, the convention of
  879.    passing a pointer to a large aggregate instead of a copy is not used.

  881.    MVS: The above appears to be true for the SH variants that do not
  882.    have an FPU, however those that have an FPU appear to copy the
  883.    aggregate argument onto the stack (and not place it in registers)
  884.    if it is larger than 16 bytes (four GP registers).

  886.    An exceptional case exists for struct arguments (and possibly other
  887.    aggregates such as arrays) if the size is larger than 4 bytes but
  888.    not a multiple of 4 bytes.  In this case the argument is never split
  889.    between the registers and the stack, but instead is copied in its
  890.    entirety onto the stack, AND also copied into as many registers as
  891.    there is room for.  In other words, space in registers permitting,
  892.    two copies of the same argument are passed in.  As far as I can tell,
  893.    only the one on the stack is used, although that may be a function
  894.    of the level of compiler optimization.  I suspect this is a compiler
  895.    bug.  Arguments of these odd sizes are left-justified within the
  896.    word (as opposed to arguments smaller than 4 bytes, which are
  897.    right-justified).

  899.    If the function is to return an aggregate type such as a struct, it
  900.    is either returned in the normal return value register R0 (if its
  901.    size is no greater than one byte), or else the caller must allocate
  902.    space into which the callee will copy the return value (if the size
  903.    is greater than one byte).  In this case, a pointer to the return
  904.    value location is passed into the callee in register R2, which does
  905.    not displace any of the other arguments passed in via registers R4
  906.    to R7.  */

  908. /* Helper function to justify value in register according to endianess.  */
  909. static const gdb_byte *
  910. ‌sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
  911. {
  912.   static gdb_byte valbuf[4];

  914.   memset (valbuf, 0, sizeof (valbuf));
  915.   if (len < 4)
  916.     {
  917.       /* value gets right-justified in the register or stack word.  */
  918.       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
  919.         memcpy (valbuf + (4 - len), value_contents (val), len);
  920.       else
  921.         memcpy (valbuf, value_contents (val), len);
  922.       return valbuf;
  923.     }
  924.   return value_contents (val);
  925. }

  927. /* Helper function to eval number of bytes to allocate on stack.  */
  928. static CORE_ADDR
  929. ‌sh_stack_allocsize (int nargs, struct value **args)
  930. {
  931.   int stack_alloc = 0;
  932.   while (nargs-- > 0)
  933.     stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
  934.   return stack_alloc;
  935. }

  937. /* Helper functions for getting the float arguments right.  Registers usage
  938.    depends on the ABI and the endianess.  The comments should enlighten how
  939.    it's intended to work.  */

  941. /* This array stores which of the float arg registers are already in use.  */
  942. ‌static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];

  944. /* This function just resets the above array to "no reg used so far".  */
  945. static void
  946. ‌sh_init_flt_argreg (void)
  947. {
  948.   memset (flt_argreg_array, 0, sizeof flt_argreg_array);
  949. }

  951. /* This function returns the next register to use for float arg passing.
  952.    It returns either a valid value between FLOAT_ARG0_REGNUM and
  953.    FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
  954.    FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.

  956.    Note that register number 0 in flt_argreg_array corresponds with the
  957.    real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
  958.    29) the parity of the register number is preserved, which is important
  959.    for the double register passing test (see the "argreg & 1" test below).  */
  960. static int
  961. ‌sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
  962. {
  963.   int argreg;

  965.   /* First search for the next free register.  */
  966.   for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
  967.        ++argreg)
  968.     if (!flt_argreg_array[argreg])
  969.       break;

  971.   /* No register left?  */
  972.   if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
  973.     return FLOAT_ARGLAST_REGNUM + 1;

  975.   if (len == 8)
  976.     {
  977.       /* Doubles are always starting in a even register number.  */
  978.       if (argreg & 1)
  979.         {
  980.           /* In gcc ABI, the skipped register is lost for further argument
  981.              passing now.  Not so in Renesas ABI.  */
  982.           if (!sh_is_renesas_calling_convention (func_type))
  983.             flt_argreg_array[argreg] = 1;

  985.           ++argreg;

  987.           /* No register left?  */
  988.           if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
  989.             return FLOAT_ARGLAST_REGNUM + 1;
  990.         }
  991.       /* Also mark the next register as used.  */
  992.       flt_argreg_array[argreg + 1] = 1;
  993.     }
  994.   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
  995.            && !sh_is_renesas_calling_convention (func_type))
  996.     {
  997.       /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ...  */
  998.       if (!flt_argreg_array[argreg + 1])
  999.         ++argreg;
  1000.     }
  1001.   flt_argreg_array[argreg] = 1;
  1002.   return FLOAT_ARG0_REGNUM + argreg;
  1003. }

  1005. /* Helper function which figures out, if a type is treated like a float type.

  1007.    The FPU ABIs have a special way how to treat types as float types.
  1008.    Structures with exactly one member, which is of type float or double, are
  1009.    treated exactly as the base types float or double:

  1011.      struct sf {
  1012.        float f;
  1013.      };

  1015.      struct sd {
  1016.        double d;
  1017.      };

  1019.    are handled the same way as just

  1021.      float f;

  1023.      double d;

  1025.    As a result, arguments of these struct types are pushed into floating point
  1026.    registers exactly as floats or doubles, using the same decision algorithm.

  1028.    The same is valid if these types are used as function return types.  The
  1029.    above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
  1030.    or even using struct convention as it is for other structs.  */

  1032. static int
  1033. ‌sh_treat_as_flt_p (struct type *type)
  1034. {
  1035.   /* Ordinary float types are obviously treated as float.  */
  1036.   if (TYPE_CODE (type) == TYPE_CODE_FLT)
  1037.     return 1;
  1038.   /* Otherwise non-struct types are not treated as float.  */
  1039.   if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
  1040.     return 0;
  1041.   /* Otherwise structs with more than one memeber are not treated as float.  */
  1042.   if (TYPE_NFIELDS (type) != 1)
  1043.     return 0;
  1044.   /* Otherwise if the type of that member is float, the whole type is
  1045.      treated as float.  */
  1046.   if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
  1047.     return 1;
  1048.   /* Otherwise it's not treated as float.  */
  1049.   return 0;
  1050. }

  1052. static CORE_ADDR
  1053. ‌sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
  1054.                         struct value *function,
  1055.                         struct regcache *regcache,
  1056.                         CORE_ADDR bp_addr, int nargs,
  1057.                         struct value **args,
  1058.                         CORE_ADDR sp, int struct_return,
  1059.                         CORE_ADDR struct_addr)
  1060. {
  1061.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1062.   int stack_offset = 0;
  1063.   int argreg = ARG0_REGNUM;
  1064.   int flt_argreg = 0;
  1065.   int argnum;
  1066.   struct type *func_type = value_type (function);
  1067.   struct type *type;
  1068.   CORE_ADDR regval;
  1069.   const gdb_byte *val;
  1070.   int len, reg_size = 0;
  1071.   int pass_on_stack = 0;
  1072.   int treat_as_flt;
  1073.   int last_reg_arg = INT_MAX;

  1075.   /* The Renesas ABI expects all varargs arguments, plus the last
  1076.      non-vararg argument to be on the stack, no matter how many
  1077.      registers have been used so far.  */
  1078.   if (sh_is_renesas_calling_convention (func_type)
  1079.       && TYPE_VARARGS (func_type))
  1080.     last_reg_arg = TYPE_NFIELDS (func_type) - 2;

  1082.   /* First force sp to a 4-byte alignment.  */
  1083.   sp = sh_frame_align (gdbarch, sp);

  1085.   /* Make room on stack for args.  */
  1086.   sp -= sh_stack_allocsize (nargs, args);

  1088.   /* Initialize float argument mechanism.  */
  1089.   sh_init_flt_argreg ();

  1091.   /* Now load as many as possible of the first arguments into
  1092.      registers, and push the rest onto the stack.  There are 16 bytes
  1093.      in four registers available.  Loop thru args from first to last.  */
  1094.   for (argnum = 0; argnum < nargs; argnum++)
  1095.     {
  1096.       type = value_type (args[argnum]);
  1097.       len = TYPE_LENGTH (type);
  1098.       val = sh_justify_value_in_reg (gdbarch, args[argnum], len);

  1100.       /* Some decisions have to be made how various types are handled.
  1101.          This also differs in different ABIs.  */
  1102.       pass_on_stack = 0;

  1104.       /* Find out the next register to use for a floating point value.  */
  1105.       treat_as_flt = sh_treat_as_flt_p (type);
  1106.       if (treat_as_flt)
  1107.         flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
  1108.       /* In Renesas ABI, long longs and aggregate types are always passed
  1109.          on stack.  */
  1110.       else if (sh_is_renesas_calling_convention (func_type)
  1111.                && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
  1112.                    || TYPE_CODE (type) == TYPE_CODE_STRUCT
  1113.                    || TYPE_CODE (type) == TYPE_CODE_UNION))
  1114.         pass_on_stack = 1;
  1115.       /* In contrast to non-FPU CPUs, arguments are never split between
  1116.          registers and stack.  If an argument doesn't fit in the remaining
  1117.          registers it's always pushed entirely on the stack.  */
  1118.       else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
  1119.         pass_on_stack = 1;

  1121.       while (len > 0)
  1122.         {
  1123.           if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
  1124.               || (!treat_as_flt && (argreg > ARGLAST_REGNUM
  1125.                                     || pass_on_stack))
  1126.               || argnum > last_reg_arg)
  1127.             {
  1128.               /* The data goes entirely on the stack, 4-byte aligned.  */
  1129.               reg_size = (len + 3) & ~3;
  1130.               write_memory (sp + stack_offset, val, reg_size);
  1131.               stack_offset += reg_size;
  1132.             }
  1133.           else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
  1134.             {
  1135.               /* Argument goes in a float argument register.  */
  1136.               reg_size = register_size (gdbarch, flt_argreg);
  1137.               regval = extract_unsigned_integer (val, reg_size, byte_order);
  1138.               /* In little endian mode, float types taking two registers
  1139.                  (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
  1140.                  be stored swapped in the argument registers.  The below
  1141.                  code first writes the first 32 bits in the next but one
  1142.                  register, increments the val and len values accordingly
  1143.                  and then proceeds as normal by writing the second 32 bits
  1144.                  into the next register.  */
  1145.               if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
  1146.                   && TYPE_LENGTH (type) == 2 * reg_size)
  1147.                 {
  1148.                   regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
  1149.                                                   regval);
  1150.                   val += reg_size;
  1151.                   len -= reg_size;
  1152.                   regval = extract_unsigned_integer (val, reg_size,
  1153.                                                      byte_order);
  1154.                 }
  1155.               regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
  1156.             }
  1157.           else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
  1158.             {
  1159.               /* there's room in a register */
  1160.               reg_size = register_size (gdbarch, argreg);
  1161.               regval = extract_unsigned_integer (val, reg_size, byte_order);
  1162.               regcache_cooked_write_unsigned (regcache, argreg++, regval);
  1163.             }
  1164.           /* Store the value one register at a time or in one step on
  1165.              stack.  */
  1166.           len -= reg_size;
  1167.           val += reg_size;
  1168.         }
  1169.     }

  1171.   if (struct_return)
  1172.     {
  1173.       if (sh_is_renesas_calling_convention (func_type))
  1174.         /* If the function uses the Renesas ABI, subtract another 4 bytes from
  1175.            the stack and store the struct return address there.  */
  1176.         write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
  1177.       else
  1178.         /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
  1179.            its own dedicated register.  */
  1180.         regcache_cooked_write_unsigned (regcache,
  1181.                                         STRUCT_RETURN_REGNUM, struct_addr);
  1182.     }

  1184.   /* Store return address.  */
  1185.   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);

  1187.   /* Update stack pointer.  */
  1188.   regcache_cooked_write_unsigned (regcache,
  1189.                                   gdbarch_sp_regnum (gdbarch), sp);

  1191.   return sp;
  1192. }

  1194. static CORE_ADDR
  1195. ‌sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
  1196.                           struct value *function,
  1197.                           struct regcache *regcache,
  1198.                           CORE_ADDR bp_addr,
  1199.                           int nargs, struct value **args,
  1200.                           CORE_ADDR sp, int struct_return,
  1201.                           CORE_ADDR struct_addr)
  1202. {
  1203.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1204.   int stack_offset = 0;
  1205.   int argreg = ARG0_REGNUM;
  1206.   int argnum;
  1207.   struct type *func_type = value_type (function);
  1208.   struct type *type;
  1209.   CORE_ADDR regval;
  1210.   const gdb_byte *val;
  1211.   int len, reg_size = 0;
  1212.   int pass_on_stack = 0;
  1213.   int last_reg_arg = INT_MAX;

  1215.   /* The Renesas ABI expects all varargs arguments, plus the last
  1216.      non-vararg argument to be on the stack, no matter how many
  1217.      registers have been used so far.  */
  1218.   if (sh_is_renesas_calling_convention (func_type)
  1219.       && TYPE_VARARGS (func_type))
  1220.     last_reg_arg = TYPE_NFIELDS (func_type) - 2;

  1222.   /* First force sp to a 4-byte alignment.  */
  1223.   sp = sh_frame_align (gdbarch, sp);

  1225.   /* Make room on stack for args.  */
  1226.   sp -= sh_stack_allocsize (nargs, args);

  1228.   /* Now load as many as possible of the first arguments into
  1229.      registers, and push the rest onto the stack.  There are 16 bytes
  1230.      in four registers available.  Loop thru args from first to last.  */
  1231.   for (argnum = 0; argnum < nargs; argnum++)
  1232.     {
  1233.       type = value_type (args[argnum]);
  1234.       len = TYPE_LENGTH (type);
  1235.       val = sh_justify_value_in_reg (gdbarch, args[argnum], len);

  1237.       /* Some decisions have to be made how various types are handled.
  1238.          This also differs in different ABIs.  */
  1239.       pass_on_stack = 0;
  1240.       /* Renesas ABI pushes doubles and long longs entirely on stack.
  1241.          Same goes for aggregate types.  */
  1242.       if (sh_is_renesas_calling_convention (func_type)
  1243.           && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
  1244.               || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
  1245.               || TYPE_CODE (type) == TYPE_CODE_STRUCT
  1246.               || TYPE_CODE (type) == TYPE_CODE_UNION))
  1247.         pass_on_stack = 1;
  1248.       while (len > 0)
  1249.         {
  1250.           if (argreg > ARGLAST_REGNUM || pass_on_stack
  1251.               || argnum > last_reg_arg)
  1252.             {
  1253.               /* The remainder of the data goes entirely on the stack,
  1254.                  4-byte aligned.  */
  1255.               reg_size = (len + 3) & ~3;
  1256.               write_memory (sp + stack_offset, val, reg_size);
  1257.               stack_offset += reg_size;
  1258.             }
  1259.           else if (argreg <= ARGLAST_REGNUM)
  1260.             {
  1261.               /* There's room in a register.  */
  1262.               reg_size = register_size (gdbarch, argreg);
  1263.               regval = extract_unsigned_integer (val, reg_size, byte_order);
  1264.               regcache_cooked_write_unsigned (regcache, argreg++, regval);
  1265.             }
  1266.           /* Store the value reg_size bytes at a time.  This means that things
  1267.              larger than reg_size bytes may go partly in registers and partly
  1268.              on the stack.  */
  1269.           len -= reg_size;
  1270.           val += reg_size;
  1271.         }
  1272.     }

  1274.   if (struct_return)
  1275.     {
  1276.       if (sh_is_renesas_calling_convention (func_type))
  1277.         /* If the function uses the Renesas ABI, subtract another 4 bytes from
  1278.            the stack and store the struct return address there.  */
  1279.         write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
  1280.       else
  1281.         /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
  1282.            its own dedicated register.  */
  1283.         regcache_cooked_write_unsigned (regcache,
  1284.                                         STRUCT_RETURN_REGNUM, struct_addr);
  1285.     }

  1287.   /* Store return address.  */
  1288.   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);

  1290.   /* Update stack pointer.  */
  1291.   regcache_cooked_write_unsigned (regcache,
  1292.                                   gdbarch_sp_regnum (gdbarch), sp);

  1294.   return sp;
  1295. }

  1297. /* Find a function's return value in the appropriate registers (in
  1298.    regbuf), and copy it into valbuf.  Extract from an array REGBUF
  1299.    containing the (raw) register state a function return value of type
  1300.    TYPE, and copy that, in virtual format, into VALBUF.  */
  1301. static void
  1302. ‌sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
  1303.                                gdb_byte *valbuf)
  1304. {
  1305.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  1306.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1307.   int len = TYPE_LENGTH (type);
  1308.   int return_register = R0_REGNUM;
  1309.   int offset;

  1311.   if (len <= 4)
  1312.     {
  1313.       ULONGEST c;

  1315.       regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
  1316.       store_unsigned_integer (valbuf, len, byte_order, c);
  1317.     }
  1318.   else if (len == 8)
  1319.     {
  1320.       int i, regnum = R0_REGNUM;
  1321.       for (i = 0; i < len; i += 4)
  1322.         regcache_raw_read (regcache, regnum++, valbuf + i);
  1323.     }
  1324.   else
  1325.     error (_("bad size for return value"));
  1326. }

  1328. static void
  1329. ‌sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
  1330.                              gdb_byte *valbuf)
  1331. {
  1332.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  1333.   if (sh_treat_as_flt_p (type))
  1334.     {
  1335.       int len = TYPE_LENGTH (type);
  1336.       int i, regnum = gdbarch_fp0_regnum (gdbarch);
  1337.       for (i = 0; i < len; i += 4)
  1338.         if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
  1339.           regcache_raw_read (regcache, regnum++,
  1340.                              valbuf + len - 4 - i);
  1341.         else
  1342.           regcache_raw_read (regcache, regnum++, valbuf + i);
  1343.     }
  1344.   else
  1345.     sh_extract_return_value_nofpu (type, regcache, valbuf);
  1346. }

  1348. /* Write into appropriate registers a function return value
  1349.    of type TYPE, given in virtual format.
  1350.    If the architecture is sh4 or sh3e, store a function's return value
  1351.    in the R0 general register or in the FP0 floating point register,
  1352.    depending on the type of the return value.  In all the other cases
  1353.    the result is stored in r0, left-justified.  */
  1354. static void
  1355. ‌sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
  1356.                              const gdb_byte *valbuf)
  1357. {
  1358.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  1359.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1360.   ULONGEST val;
  1361.   int len = TYPE_LENGTH (type);

  1363.   if (len <= 4)
  1364.     {
  1365.       val = extract_unsigned_integer (valbuf, len, byte_order);
  1366.       regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
  1367.     }
  1368.   else
  1369.     {
  1370.       int i, regnum = R0_REGNUM;
  1371.       for (i = 0; i < len; i += 4)
  1372.         regcache_raw_write (regcache, regnum++, valbuf + i);
  1373.     }
  1374. }

  1376. static void
  1377. ‌sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
  1378.                            const gdb_byte *valbuf)
  1379. {
  1380.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  1381.   if (sh_treat_as_flt_p (type))
  1382.     {
  1383.       int len = TYPE_LENGTH (type);
  1384.       int i, regnum = gdbarch_fp0_regnum (gdbarch);
  1385.       for (i = 0; i < len; i += 4)
  1386.         if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
  1387.           regcache_raw_write (regcache, regnum++,
  1388.                               valbuf + len - 4 - i);
  1389.         else
  1390.           regcache_raw_write (regcache, regnum++, valbuf + i);
  1391.     }
  1392.   else
  1393.     sh_store_return_value_nofpu (type, regcache, valbuf);
  1394. }

  1396. static enum return_value_convention
  1397. ‌sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function,
  1398.                        struct type *type, struct regcache *regcache,
  1399.                        gdb_byte *readbuf, const gdb_byte *writebuf)
  1400. {
  1401.   struct type *func_type = function ? value_type (function) : NULL;

  1403.   if (sh_use_struct_convention_nofpu (
  1404.           sh_is_renesas_calling_convention (func_type), type))
  1405.     return RETURN_VALUE_STRUCT_CONVENTION;
  1406.   if (writebuf)
  1407.     sh_store_return_value_nofpu (type, regcache, writebuf);
  1408.   else if (readbuf)
  1409.     sh_extract_return_value_nofpu (type, regcache, readbuf);
  1410.   return RETURN_VALUE_REGISTER_CONVENTION;
  1411. }

  1413. static enum return_value_convention
  1414. ‌sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function,
  1415.                      struct type *type, struct regcache *regcache,
  1416.                      gdb_byte *readbuf, const gdb_byte *writebuf)
  1417. {
  1418.   struct type *func_type = function ? value_type (function) : NULL;

  1420.   if (sh_use_struct_convention (
  1421.         sh_is_renesas_calling_convention (func_type), type))
  1422.     return RETURN_VALUE_STRUCT_CONVENTION;
  1423.   if (writebuf)
  1424.     sh_store_return_value_fpu (type, regcache, writebuf);
  1425.   else if (readbuf)
  1426.     sh_extract_return_value_fpu (type, regcache, readbuf);
  1427.   return RETURN_VALUE_REGISTER_CONVENTION;
  1428. }

  1430. static struct type *
  1431. ‌sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
  1432. {
  1433.   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
  1434.        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
  1435.     return builtin_type (gdbarch)->builtin_float;
  1436.   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
  1437.     return builtin_type (gdbarch)->builtin_double;
  1438.   else
  1439.     return builtin_type (gdbarch)->builtin_int;
  1440. }

  1442. /* Return the GDB type object for the "standard" data type
  1443.    of data in register N.  */
  1444. static struct type *
  1445. ‌sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
  1446. {
  1447.   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
  1448.        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
  1449.     return builtin_type (gdbarch)->builtin_float;
  1450.   else
  1451.     return builtin_type (gdbarch)->builtin_int;
  1452. }

  1454. static struct type *
  1455. ‌sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
  1456. {
  1457.   return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
  1458.                                   0, high);
  1459. }

  1461. static struct type *
  1462. ‌sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
  1463. {
  1464.   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
  1465.        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
  1466.     return builtin_type (gdbarch)->builtin_float;
  1467.   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
  1468.     return builtin_type (gdbarch)->builtin_double;
  1469.   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
  1470.     return sh_sh4_build_float_register_type (gdbarch, 3);
  1471.   else
  1472.     return builtin_type (gdbarch)->builtin_int;
  1473. }

  1475. static struct type *
  1476. ‌sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
  1477. {
  1478.   return builtin_type (gdbarch)->builtin_int;
  1479. }

  1481. /* Is a register in a reggroup?
  1482.    The default code in reggroup.c doesn't identify system registers, some
  1483.    float registers or any of the vector registers.
  1484.    TODO: sh2a and dsp registers.  */
  1485. static int
  1486. ‌sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  1487.                         struct reggroup *reggroup)
  1488. {
  1489.   if (gdbarch_register_name (gdbarch, regnum) == NULL
  1490.       || *gdbarch_register_name (gdbarch, regnum) == '\0')
  1491.     return 0;

  1493.   if (reggroup == float_reggroup
  1494.       && (regnum == FPUL_REGNUM
  1495.           || regnum == FPSCR_REGNUM))
  1496.     return 1;

  1498.   if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
  1499.     {
  1500.       if (reggroup == vector_reggroup || reggroup == float_reggroup)
  1501.         return 1;
  1502.       if (reggroup == general_reggroup)
  1503.         return 0;
  1504.     }

  1506.   if (regnum == VBR_REGNUM
  1507.       || regnum == SR_REGNUM
  1508.       || regnum == FPSCR_REGNUM
  1509.       || regnum == SSR_REGNUM
  1510.       || regnum == SPC_REGNUM)
  1511.     {
  1512.       if (reggroup == system_reggroup)
  1513.         return 1;
  1514.       if (reggroup == general_reggroup)
  1515.         return 0;
  1516.     }

  1518.   /* The default code can cope with any other registers.  */
  1519.   return default_register_reggroup_p (gdbarch, regnum, reggroup);
  1520. }

  1522. /* On the sh4, the DRi pseudo registers are problematic if the target
  1523.    is little endian.  When the user writes one of those registers, for
  1524.    instance with 'set var $dr0=1', we want the double to be stored
  1525.    like this:
  1526.    fr0 = 0x00 0x00 0xf0 0x3f
  1527.    fr1 = 0x00 0x00 0x00 0x00

  1529.    This corresponds to little endian byte order & big endian word
  1530.    order.  However if we let gdb write the register w/o conversion, it
  1531.    will write fr0 and fr1 this way:
  1532.    fr0 = 0x00 0x00 0x00 0x00
  1533.    fr1 = 0x00 0x00 0xf0 0x3f
  1534.    because it will consider fr0 and fr1 as a single LE stretch of memory.

  1536.    To achieve what we want we must force gdb to store things in
  1537.    floatformat_ieee_double_littlebyte_bigword (which is defined in
  1538.    include/floatformat.h and libiberty/floatformat.c.

  1540.    In case the target is big endian, there is no problem, the
  1541.    raw bytes will look like:
  1542.    fr0 = 0x3f 0xf0 0x00 0x00
  1543.    fr1 = 0x00 0x00 0x00 0x00

  1545.    The other pseudo registers (the FVs) also don't pose a problem
  1546.    because they are stored as 4 individual FP elements.  */

  1548. static void
  1549. ‌sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
  1550.                                 struct type *type, gdb_byte *from, gdb_byte *to)
  1551. {
  1552.   if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
  1553.     {
  1554.       /* It is a no-op.  */
  1555.       memcpy (to, from, register_size (gdbarch, regnum));
  1556.       return;
  1557.     }

  1559.   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
  1560.     {
  1561.       DOUBLEST val;
  1562.       floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
  1563.                                from, &val);
  1564.       store_typed_floating (to, type, val);
  1565.     }
  1566.   else
  1567.     error
  1568.       ("sh_register_convert_to_virtual called with non DR register number");
  1569. }

  1571. static void
  1572. ‌sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
  1573.                             int regnum, const gdb_byte *from, gdb_byte *to)
  1574. {
  1575.   if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
  1576.     {
  1577.       /* It is a no-op.  */
  1578.       memcpy (to, from, register_size (gdbarch, regnum));
  1579.       return;
  1580.     }

  1582.   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
  1583.     {
  1584.       DOUBLEST val = extract_typed_floating (from, type);
  1585.       floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
  1586.                                  &val, to);
  1587.     }
  1588.   else
  1589.     error (_("sh_register_convert_to_raw called with non DR register number"));
  1590. }

  1592. /* For vectors of 4 floating point registers.  */
  1593. static int
  1594. ‌fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
  1595. {
  1596.   int fp_regnum;

  1598.   fp_regnum = gdbarch_fp0_regnum (gdbarch)
  1599.               + (fv_regnum - FV0_REGNUM) * 4;
  1600.   return fp_regnum;
  1601. }

  1603. /* For double precision floating point registers, i.e 2 fp regs.  */
  1604. static int
  1605. ‌dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
  1606. {
  1607.   int fp_regnum;

  1609.   fp_regnum = gdbarch_fp0_regnum (gdbarch)
  1610.               + (dr_regnum - DR0_REGNUM) * 2;
  1611.   return fp_regnum;
  1612. }

  1614. /* Concatenate PORTIONS contiguous raw registers starting at
  1615.    BASE_REGNUM into BUFFER.  */

  1617. static enum register_status
  1618. ‌pseudo_register_read_portions (struct gdbarch *gdbarch,
  1619.                                struct regcache *regcache,
  1620.                                int portions,
  1621.                                int base_regnum, gdb_byte *buffer)
  1622. {
  1623.   int portion;

  1625.   for (portion = 0; portion < portions; portion++)
  1626.     {
  1627.       enum register_status status;
  1628.       gdb_byte *b;

  1630.       b = buffer + register_size (gdbarch, base_regnum) * portion;
  1631.       status = regcache_raw_read (regcache, base_regnum + portion, b);
  1632.       if (status != REG_VALID)
  1633.         return status;
  1634.     }

  1636.   return REG_VALID;
  1637. }

  1639. static enum register_status
  1640. ‌sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
  1641.                          int reg_nr, gdb_byte *buffer)
  1642. {
  1643.   int base_regnum;
  1644.   gdb_byte temp_buffer[MAX_REGISTER_SIZE];
  1645.   enum register_status status;

  1647.   if (reg_nr == PSEUDO_BANK_REGNUM)
  1648.     return regcache_raw_read (regcache, BANK_REGNUM, buffer);
  1649.   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
  1650.     {
  1651.       base_regnum = dr_reg_base_num (gdbarch, reg_nr);

  1653.       /* Build the value in the provided buffer.  */
  1654.       /* Read the real regs for which this one is an alias.  */
  1655.       status = pseudo_register_read_portions (gdbarch, regcache,
  1656.                                               2, base_regnum, temp_buffer);
  1657.       if (status == REG_VALID)
  1658.         {
  1659.           /* We must pay attention to the endiannes. */
  1660.           sh_register_convert_to_virtual (gdbarch, reg_nr,
  1661.                                           register_type (gdbarch, reg_nr),
  1662.                                           temp_buffer, buffer);
  1663.         }
  1664.       return status;
  1665.     }
  1666.   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
  1667.     {
  1668.       base_regnum = fv_reg_base_num (gdbarch, reg_nr);

  1670.       /* Read the real regs for which this one is an alias.  */
  1671.       return pseudo_register_read_portions (gdbarch, regcache,
  1672.                                             4, base_regnum, buffer);
  1673.     }
  1674.   else
  1675.     gdb_assert_not_reached ("invalid pseudo register number");
  1676. }

  1678. static void
  1679. ‌sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
  1680.                           int reg_nr, const gdb_byte *buffer)
  1681. {
  1682.   int base_regnum, portion;
  1683.   gdb_byte temp_buffer[MAX_REGISTER_SIZE];

  1685.   if (reg_nr == PSEUDO_BANK_REGNUM)
  1686.     {
  1687.       /* When the bank register is written to, the whole register bank
  1688.          is switched and all values in the bank registers must be read
  1689.          from the target/sim again.  We're just invalidating the regcache
  1690.          so that a re-read happens next time it's necessary.  */
  1691.       int bregnum;

  1693.       regcache_raw_write (regcache, BANK_REGNUM, buffer);
  1694.       for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
  1695.         regcache_invalidate (regcache, bregnum);
  1696.     }
  1697.   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
  1698.     {
  1699.       base_regnum = dr_reg_base_num (gdbarch, reg_nr);

  1701.       /* We must pay attention to the endiannes.  */
  1702.       sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
  1703.                                   reg_nr, buffer, temp_buffer);

  1705.       /* Write the real regs for which this one is an alias.  */
  1706.       for (portion = 0; portion < 2; portion++)
  1707.         regcache_raw_write (regcache, base_regnum + portion,
  1708.                             (temp_buffer
  1709.                              + register_size (gdbarch,
  1710.                                               base_regnum) * portion));
  1711.     }
  1712.   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
  1713.     {
  1714.       base_regnum = fv_reg_base_num (gdbarch, reg_nr);

  1716.       /* Write the real regs for which this one is an alias.  */
  1717.       for (portion = 0; portion < 4; portion++)
  1718.         regcache_raw_write (regcache, base_regnum + portion,
  1719.                             (buffer
  1720.                              + register_size (gdbarch,
  1721.                                               base_regnum) * portion));
  1722.     }
  1723. }

  1725. static int
  1726. ‌sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
  1727. {
  1728.   if (legacy_register_sim_regno (gdbarch, nr) < 0)
  1729.     return legacy_register_sim_regno (gdbarch, nr);
  1730.   if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
  1731.     return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
  1732.   if (nr == MOD_REGNUM)
  1733.     return SIM_SH_MOD_REGNUM;
  1734.   if (nr == RS_REGNUM)
  1735.     return SIM_SH_RS_REGNUM;
  1736.   if (nr == RE_REGNUM)
  1737.     return SIM_SH_RE_REGNUM;
  1738.   if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
  1739.     return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
  1740.   return nr;
  1741. }

  1743. static int
  1744. ‌sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
  1745. {
  1746.   switch (nr)
  1747.     {
  1748.       case TBR_REGNUM:
  1749.         return SIM_SH_TBR_REGNUM;
  1750.       case IBNR_REGNUM:
  1751.         return SIM_SH_IBNR_REGNUM;
  1752.       case IBCR_REGNUM:
  1753.         return SIM_SH_IBCR_REGNUM;
  1754.       case BANK_REGNUM:
  1755.         return SIM_SH_BANK_REGNUM;
  1756.       case MACLB_REGNUM:
  1757.         return SIM_SH_BANK_MACL_REGNUM;
  1758.       case GBRB_REGNUM:
  1759.         return SIM_SH_BANK_GBR_REGNUM;
  1760.       case PRB_REGNUM:
  1761.         return SIM_SH_BANK_PR_REGNUM;
  1762.       case IVNB_REGNUM:
  1763.         return SIM_SH_BANK_IVN_REGNUM;
  1764.       case MACHB_REGNUM:
  1765.         return SIM_SH_BANK_MACH_REGNUM;
  1766.       default:
  1767.         break;
  1768.     }
  1769.   return legacy_register_sim_regno (gdbarch, nr);
  1770. }

  1772. /* Set up the register unwinding such that call-clobbered registers are
  1773.    not displayed in frames >0 because the true value is not certain.
  1774.    The 'undefined' registers will show up as 'not available' unless the
  1775.    CFI says otherwise.

  1777.    This function is currently set up for SH4 and compatible only.  */

  1779. static void
  1780. ‌sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
  1781.                           struct dwarf2_frame_state_reg *reg,
  1782.                           struct frame_info *this_frame)
  1783. {
  1784.   /* Mark the PC as the destination for the return address.  */
  1785.   if (regnum == gdbarch_pc_regnum (gdbarch))
  1786.     reg->how = DWARF2_FRAME_REG_RA;

  1788.   /* Mark the stack pointer as the call frame address.  */
  1789.   else if (regnum == gdbarch_sp_regnum (gdbarch))
  1790.     reg->how = DWARF2_FRAME_REG_CFA;

  1792.   /* The above was taken from the default init_reg in dwarf2-frame.c
  1793.      while the below is SH specific.  */

  1795.   /* Caller save registers.  */
  1796.   else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
  1797.            || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
  1798.            || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
  1799.            || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
  1800.            || (regnum == MACH_REGNUM)
  1801.            || (regnum == MACL_REGNUM)
  1802.            || (regnum == FPUL_REGNUM)
  1803.            || (regnum == SR_REGNUM))
  1804.     reg->how = DWARF2_FRAME_REG_UNDEFINED;

  1806.   /* Callee save registers.  */
  1807.   else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
  1808.            || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
  1809.            || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
  1810.            || (regnum == FV0_REGNUM+3))
  1811.     reg->how = DWARF2_FRAME_REG_SAME_VALUE;

  1813.   /* Other registers.  These are not in the ABI and may or may not
  1814.      mean anything in frames >0 so don't show them.  */
  1815.   else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
  1816.            || (regnum == GBR_REGNUM)
  1817.            || (regnum == VBR_REGNUM)
  1818.            || (regnum == FPSCR_REGNUM)
  1819.            || (regnum == SSR_REGNUM)
  1820.            || (regnum == SPC_REGNUM))
  1821.     reg->how = DWARF2_FRAME_REG_UNDEFINED;
  1822. }

  1824. static struct sh_frame_cache *
  1825. ‌sh_alloc_frame_cache (void)
  1826. {
  1827.   struct sh_frame_cache *cache;
  1828.   int i;

  1830.   cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);

  1832.   /* Base address.  */
  1833.   cache->base = 0;
  1834.   cache->saved_sp = 0;
  1835.   cache->sp_offset = 0;
  1836.   cache->pc = 0;

  1838.   /* Frameless until proven otherwise.  */
  1839.   cache->uses_fp = 0;

  1841.   /* Saved registers.  We initialize these to -1 since zero is a valid
  1842.      offset (that's where fp is supposed to be stored).  */
  1843.   for (i = 0; i < SH_NUM_REGS; i++)
  1844.     {
  1845.       cache->saved_regs[i] = -1;
  1846.     }

  1848.   return cache;
  1849. }

  1851. static struct sh_frame_cache *
  1852. ‌sh_frame_cache (struct frame_info *this_frame, void **this_cache)
  1853. {
  1854.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  1855.   struct sh_frame_cache *cache;
  1856.   CORE_ADDR current_pc;
  1857.   int i;

  1859.   if (*this_cache)
  1860.     return *this_cache;

  1862.   cache = sh_alloc_frame_cache ();
  1863.   *this_cache = cache;

  1865.   /* In principle, for normal frames, fp holds the frame pointer,
  1866.      which holds the base address for the current stack frame.
  1867.      However, for functions that don't need it, the frame pointer is
  1868.      optional.  For these "frameless" functions the frame pointer is
  1869.      actually the frame pointer of the calling frame.  */
  1870.   cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
  1871.   if (cache->base == 0)
  1872.     return cache;

  1874.   cache->pc = get_frame_func (this_frame);
  1875.   current_pc = get_frame_pc (this_frame);
  1876.   if (cache->pc != 0)
  1877.     {
  1878.       ULONGEST fpscr;

  1880.       /* Check for the existence of the FPSCR register.         If it exists,
  1881.          fetch its value for use in prologue analysis.        Passing a zero
  1882.          value is the best choice for architecture variants upon which
  1883.          there's no FPSCR register.  */
  1884.       if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup))
  1885.         fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
  1886.       else
  1887.         fpscr = 0;

  1889.       sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
  1890.     }

  1892.   if (!cache->uses_fp)
  1893.     {
  1894.       /* We didn't find a valid frame, which means that CACHE->base
  1895.          currently holds the frame pointer for our calling frame.  If
  1896.          we're at the start of a function, or somewhere half-way its
  1897.          prologue, the function's frame probably hasn't been fully
  1898.          setup yet.  Try to reconstruct the base address for the stack
  1899.          frame by looking at the stack pointer.  For truly "frameless"
  1900.          functions this might work too.  */
  1901.       cache->base = get_frame_register_unsigned
  1902.                      (this_frame, gdbarch_sp_regnum (gdbarch));
  1903.     }

  1905.   /* Now that we have the base address for the stack frame we can
  1906.      calculate the value of sp in the calling frame.  */
  1907.   cache->saved_sp = cache->base + cache->sp_offset;

  1909.   /* Adjust all the saved registers such that they contain addresses
  1910.      instead of offsets.  */
  1911.   for (i = 0; i < SH_NUM_REGS; i++)
  1912.     if (cache->saved_regs[i] != -1)
  1913.       cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;

  1915.   return cache;
  1916. }

  1918. static struct value *
  1919. ‌sh_frame_prev_register (struct frame_info *this_frame,
  1920.                         void **this_cache, int regnum)
  1921. {
  1922.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  1923.   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);

  1925.   gdb_assert (regnum >= 0);

  1927.   if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
  1928.     return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);

  1930.   /* The PC of the previous frame is stored in the PR register of
  1931.      the current frame.  Frob regnum so that we pull the value from
  1932.      the correct place.  */
  1933.   if (regnum == gdbarch_pc_regnum (gdbarch))
  1934.     regnum = PR_REGNUM;

  1936.   if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
  1937.     return frame_unwind_got_memory (this_frame, regnum,
  1938.                                     cache->saved_regs[regnum]);

  1940.   return frame_unwind_got_register (this_frame, regnum, regnum);
  1941. }

  1943. static void
  1944. ‌sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
  1945.                   struct frame_id *this_id)
  1946. {
  1947.   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);

  1949.   /* This marks the outermost frame.  */
  1950.   if (cache->base == 0)
  1951.     return;

  1953.   *this_id = frame_id_build (cache->saved_sp, cache->pc);
  1954. }

  1956. ‌static const struct frame_unwind sh_frame_unwind = {
  1957.   NORMAL_FRAME,
  1958.   default_frame_unwind_stop_reason,
  1959.   sh_frame_this_id,
  1960.   sh_frame_prev_register,
  1961.   NULL,
  1962.   default_frame_sniffer
  1963. };

  1965. static CORE_ADDR
  1966. ‌sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
  1967. {
  1968.   return frame_unwind_register_unsigned (next_frame,
  1969.                                          gdbarch_sp_regnum (gdbarch));
  1970. }

  1972. static CORE_ADDR
  1973. ‌sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
  1974. {
  1975.   return frame_unwind_register_unsigned (next_frame,
  1976.                                          gdbarch_pc_regnum (gdbarch));
  1977. }

  1979. static struct frame_id
  1980. ‌sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
  1981. {
  1982.   CORE_ADDR sp = get_frame_register_unsigned (this_frame,
  1983.                                               gdbarch_sp_regnum (gdbarch));
  1984.   return frame_id_build (sp, get_frame_pc (this_frame));
  1985. }

  1987. static CORE_ADDR
  1988. ‌sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
  1989. {
  1990.   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);

  1992.   return cache->base;
  1993. }

  1995. ‌static const struct frame_base sh_frame_base = {
  1996.   &sh_frame_unwind,
  1997.   sh_frame_base_address,
  1998.   sh_frame_base_address,
  1999.   sh_frame_base_address
  2000. };

  2002. static struct sh_frame_cache *
  2003. ‌sh_make_stub_cache (struct frame_info *this_frame)
  2004. {
  2005.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  2006.   struct sh_frame_cache *cache;

  2008.   cache = sh_alloc_frame_cache ();

  2010.   cache->saved_sp
  2011.     = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));

  2013.   return cache;
  2014. }

  2016. static void
  2017. ‌sh_stub_this_id (struct frame_info *this_frame, void **this_cache,
  2018.                  struct frame_id *this_id)
  2019. {
  2020.   struct sh_frame_cache *cache;

  2022.   if (*this_cache == NULL)
  2023.     *this_cache = sh_make_stub_cache (this_frame);
  2024.   cache = *this_cache;

  2026.   *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame));
  2027. }

  2029. static int
  2030. ‌sh_stub_unwind_sniffer (const struct frame_unwind *self,
  2031.                         struct frame_info *this_frame,
  2032.                         void **this_prologue_cache)
  2033. {
  2034.   CORE_ADDR addr_in_block;

  2036.   addr_in_block = get_frame_address_in_block (this_frame);
  2037.   if (in_plt_section (addr_in_block))
  2038.     return 1;

  2040.   return 0;
  2041. }

  2043. ‌static const struct frame_unwind sh_stub_unwind =
  2044. {
  2045.   NORMAL_FRAME,
  2046.   default_frame_unwind_stop_reason,
  2047.   sh_stub_this_id,
  2048.   sh_frame_prev_register,
  2049.   NULL,
  2050.   sh_stub_unwind_sniffer
  2051. };

  2053. /* The epilogue is defined here as the area at the end of a function,
  2054.    either on the `ret' instruction itself or after an instruction which
  2055.    destroys the function's stack frame.  */
  2056. static int
  2057. ‌sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
  2058. {
  2059.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  2060.   CORE_ADDR func_addr = 0, func_end = 0;

  2062.   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
  2063.     {
  2064.       ULONGEST inst;
  2065.       /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
  2066.          for a nop and some fixed data (e.g. big offsets) which are
  2067.          unfortunately also treated as part of the function (which
  2068.          means, they are below func_end.  */
  2069.       CORE_ADDR addr = func_end - 28;
  2070.       if (addr < func_addr + 4)
  2071.         addr = func_addr + 4;
  2072.       if (pc < addr)
  2073.         return 0;

  2075.       /* First search forward until hitting an rts.  */
  2076.       while (addr < func_end
  2077.              && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
  2078.         addr += 2;
  2079.       if (addr >= func_end)
  2080.         return 0;

  2082.       /* At this point we should find a mov.l @r15+,r14 instruction,
  2083.          either before or after the rts.  If not, then the function has
  2084.          probably no "normal" epilogue and we bail out here.  */
  2085.       inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
  2086.       if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
  2087.                                                        byte_order)))
  2088.         addr -= 2;
  2089.       else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
  2090.                                                              byte_order)))
  2091.         return 0;

  2093.       inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);

  2095.       /* Step over possible lds.l @r15+,macl.  */
  2096.       if (IS_MACL_LDS (inst))
  2097.         {
  2098.           addr -= 2;
  2099.           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
  2100.         }

  2102.       /* Step over possible lds.l @r15+,pr.  */
  2103.       if (IS_LDS (inst))
  2104.         {
  2105.           addr -= 2;
  2106.           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
  2107.         }

  2109.       /* Step over possible mov r14,r15.  */
  2110.       if (IS_MOV_FP_SP (inst))
  2111.         {
  2112.           addr -= 2;
  2113.           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
  2114.         }

  2116.       /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
  2117.          instructions.  */
  2118.       while (addr > func_addr + 4
  2119.              && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
  2120.         {
  2121.           addr -= 2;
  2122.           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
  2123.         }

  2125.       /* On SH2a check if the previous instruction was perhaps a MOVI20.
  2126.          That's allowed for the epilogue.  */
  2127.       if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
  2128.            || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
  2129.           && addr > func_addr + 6
  2130.           && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
  2131.                                                       byte_order)))
  2132.         addr -= 4;

  2134.       if (pc >= addr)
  2135.         return 1;
  2136.     }
  2137.   return 0;
  2138. }


  2141. /* Supply register REGNUM from the buffer specified by REGS and LEN
  2142.    in the register set REGSET to register cache REGCACHE.
  2143.    REGTABLE specifies where each register can be found in REGS.
  2144.    If REGNUM is -1, do this for all registers in REGSET.  */

  2146. void
  2147. ‌sh_corefile_supply_regset (const struct regset *regset,
  2148.                            struct regcache *regcache,
  2149.                            int regnum, const void *regs, size_t len)
  2150. {
  2151.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  2152.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  2153.   const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
  2154.                                              ? tdep->core_gregmap
  2155.                                              : tdep->core_fpregmap);
  2156.   int i;

  2158.   for (i = 0; regmap[i].regnum != -1; i++)
  2159.     {
  2160.       if ((regnum == -1 || regnum == regmap[i].regnum)
  2161.           && regmap[i].offset + 4 <= len)
  2162.         regcache_raw_supply (regcache, regmap[i].regnum,
  2163.                              (char *)regs + regmap[i].offset);
  2164.     }
  2165. }

  2167. /* Collect register REGNUM in the register set REGSET from register cache
  2168.    REGCACHE into the buffer specified by REGS and LEN.
  2169.    REGTABLE specifies where each register can be found in REGS.
  2170.    If REGNUM is -1, do this for all registers in REGSET.  */

  2172. void
  2173. ‌sh_corefile_collect_regset (const struct regset *regset,
  2174.                             const struct regcache *regcache,
  2175.                             int regnum, void *regs, size_t len)
  2176. {
  2177.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  2178.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  2179.   const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
  2180.                                              ? tdep->core_gregmap
  2181.                                              : tdep->core_fpregmap);
  2182.   int i;

  2184.   for (i = 0; regmap[i].regnum != -1; i++)
  2185.     {
  2186.       if ((regnum == -1 || regnum == regmap[i].regnum)
  2187.           && regmap[i].offset + 4 <= len)
  2188.         regcache_raw_collect (regcache, regmap[i].regnum,
  2189.                               (char *)regs + regmap[i].offset);
  2190.     }
  2191. }

  2193. /* The following two regsets have the same contents, so it is tempting to
  2194.    unify them, but they are distiguished by their address, so don't.  */

  2196. ‌const struct regset sh_corefile_gregset =
  2197. {
  2198.   NULL,
  2199.   sh_corefile_supply_regset,
  2200.   sh_corefile_collect_regset
  2201. };

  2203. ‌static const struct regset sh_corefile_fpregset =
  2204. {
  2205.   NULL,
  2206.   sh_corefile_supply_regset,
  2207.   sh_corefile_collect_regset
  2208. };

  2210. static void
  2211. ‌sh_iterate_over_regset_sections (struct gdbarch *gdbarch,
  2212.                                  iterate_over_regset_sections_cb *cb,
  2213.                                  void *cb_data,
  2214.                                  const struct regcache *regcache)
  2215. {
  2216.   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

  2218.   if (tdep->core_gregmap != NULL)
  2219.     cb (".reg", tdep->sizeof_gregset, &sh_corefile_gregset, NULL, cb_data);

  2221.   if (tdep->core_fpregmap != NULL)
  2222.     cb (".reg2", tdep->sizeof_fpregset, &sh_corefile_fpregset, NULL, cb_data);
  2223. }

  2225. /* This is the implementation of gdbarch method
  2226.    return_in_first_hidden_param_p.  */

  2228. static int
  2229. ‌sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch,
  2230.                                      struct type *type)
  2231. {
  2232.   return 0;
  2233. }



  2237. static struct gdbarch *
  2238. ‌sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
  2239. {
  2240.   struct gdbarch *gdbarch;
  2241.   struct gdbarch_tdep *tdep;

  2243.   /* SH5 is handled entirely in sh64-tdep.c.  */
  2244.   if (info.bfd_arch_info->mach == bfd_mach_sh5)
  2245.     return sh64_gdbarch_init (info, arches);

  2247.   /* If there is already a candidate, use it.  */
  2248.   arches = gdbarch_list_lookup_by_info (arches, &info);
  2249.   if (arches != NULL)
  2250.     return arches->gdbarch;

  2252.   /* None found, create a new architecture from the information
  2253.      provided.  */
  2254.   tdep = XCNEW (struct gdbarch_tdep);
  2255.   gdbarch = gdbarch_alloc (&info, tdep);

  2257.   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
  2258.   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  2259.   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  2260.   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
  2261.   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  2262.   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
  2263.   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
  2264.   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);

  2266.   set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
  2267.   set_gdbarch_sp_regnum (gdbarch, 15);
  2268.   set_gdbarch_pc_regnum (gdbarch, 16);
  2269.   set_gdbarch_fp0_regnum (gdbarch, -1);
  2270.   set_gdbarch_num_pseudo_regs (gdbarch, 0);

  2272.   set_gdbarch_register_type (gdbarch, sh_default_register_type);
  2273.   set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);

  2275.   set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);

  2277.   set_gdbarch_print_insn (gdbarch, print_insn_sh);
  2278.   set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);

  2280.   set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);

  2282.   set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
  2283.   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);

  2285.   set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
  2286.   set_gdbarch_return_in_first_hidden_param_p (gdbarch,
  2287.                                               sh_return_in_first_hidden_param_p);

  2289.   set_gdbarch_believe_pcc_promotion (gdbarch, 1);

  2291.   set_gdbarch_frame_align (gdbarch, sh_frame_align);
  2292.   set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
  2293.   set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
  2294.   set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
  2295.   frame_base_set_default (gdbarch, &sh_frame_base);

  2297.   set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);

  2299.   dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);

  2301.   set_gdbarch_iterate_over_regset_sections
  2302.     (gdbarch, sh_iterate_over_regset_sections);

  2304.   switch (info.bfd_arch_info->mach)
  2305.     {
  2306.     case bfd_mach_sh:
  2307.       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
  2308.       break;

  2310.     case bfd_mach_sh2:
  2311.       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
  2312.       break;

  2314.     case bfd_mach_sh2e:
  2315.       /* doubles on sh2e and sh3e are actually 4 byte.  */
  2316.       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  2317.       set_gdbarch_double_format (gdbarch, floatformats_ieee_single);

  2319.       set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
  2320.       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
  2321.       set_gdbarch_fp0_regnum (gdbarch, 25);
  2322.       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
  2323.       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
  2324.       break;

  2326.     case bfd_mach_sh2a:
  2327.       set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
  2328.       set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
  2329.       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);

  2331.       set_gdbarch_fp0_regnum (gdbarch, 25);
  2332.       set_gdbarch_num_pseudo_regs (gdbarch, 9);
  2333.       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
  2334.       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
  2335.       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
  2336.       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
  2337.       break;

  2339.     case bfd_mach_sh2a_nofpu:
  2340.       set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
  2341.       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);

  2343.       set_gdbarch_num_pseudo_regs (gdbarch, 1);
  2344.       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
  2345.       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
  2346.       break;

  2348.     case bfd_mach_sh_dsp:
  2349.       set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
  2350.       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
  2351.       break;

  2353.     case bfd_mach_sh3:
  2354.     case bfd_mach_sh3_nommu:
  2355.     case bfd_mach_sh2a_nofpu_or_sh3_nommu:
  2356.       set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
  2357.       break;

  2359.     case bfd_mach_sh3e:
  2360.     case bfd_mach_sh2a_or_sh3e:
  2361.       /* doubles on sh2e and sh3e are actually 4 byte.  */
  2362.       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
  2363.       set_gdbarch_double_format (gdbarch, floatformats_ieee_single);

  2365.       set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
  2366.       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
  2367.       set_gdbarch_fp0_regnum (gdbarch, 25);
  2368.       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
  2369.       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
  2370.       break;

  2372.     case bfd_mach_sh3_dsp:
  2373.       set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
  2374.       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
  2375.       break;

  2377.     case bfd_mach_sh4:
  2378.     case bfd_mach_sh4a:
  2379.     case bfd_mach_sh2a_or_sh4:
  2380.       set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
  2381.       set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
  2382.       set_gdbarch_fp0_regnum (gdbarch, 25);
  2383.       set_gdbarch_num_pseudo_regs (gdbarch, 13);
  2384.       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
  2385.       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
  2386.       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
  2387.       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
  2388.       break;

  2390.     case bfd_mach_sh4_nofpu:
  2391.     case bfd_mach_sh4a_nofpu:
  2392.     case bfd_mach_sh4_nommu_nofpu:
  2393.     case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
  2394.       set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
  2395.       break;

  2397.     case bfd_mach_sh4al_dsp:
  2398.       set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
  2399.       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
  2400.       break;

  2402.     default:
  2403.       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
  2404.       break;
  2405.     }

  2407.   /* Hook in ABI-specific overrides, if they have been registered.  */
  2408.   gdbarch_init_osabi (info, gdbarch);

  2410.   dwarf2_append_unwinders (gdbarch);
  2411.   frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind);
  2412.   frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);

  2414.   return gdbarch;
  2415. }

  2417. static void
  2418. ‌show_sh_command (char *args, int from_tty)
  2419. {
  2420.   help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
  2421. }

  2423. static void
  2424. ‌set_sh_command (char *args, int from_tty)
  2425. {
  2426.   printf_unfiltered
  2427.     ("\"set sh\" must be followed by an appropriate subcommand.\n");
  2428.   help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
  2429. }

  2431. extern initialize_file_ftype _initialize_sh_tdep;  /* -Wmissing-prototypes */

  2433. void
  2434. ‌_initialize_sh_tdep (void)
  2435. {
  2436.   gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);

  2438.   add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
  2439.                   &setshcmdlist, "set sh ", 0, &setlist);
  2440.   add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
  2441.                   &showshcmdlist, "show sh ", 0, &showlist);

  2443.   add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
  2444.                         &sh_active_calling_convention,
  2445.                         _("Set calling convention used when calling target "
  2446.                           "functions from GDB."),
  2447.                         _("Show calling convention used when calling target "
  2448.                           "functions from GDB."),
  2449.                         _("gcc       - Use GCC calling convention (default).\n"
  2450.                           "renesas   - Enforce Renesas calling convention."),
  2451.                         NULL, NULL,
  2452.                         &setshcmdlist, &showshcmdlist);
  2453. }