gdb/m32r-tdep.c - gdb

Global variables defined

Data types defined

Functions defined

Macros defined

Source code

  1. /* Target-dependent code for Renesas M32R, for GDB.

  3.    Copyright (C) 1996-2015 Free Software Foundation, Inc.

  5.    This file is part of GDB.

  7.    This program is free software; you can redistribute it and/or modify
  8.    it under the terms of the GNU General Public License as published by
  9.    the Free Software Foundation; either version 3 of the License, or
  10.    (at your option) any later version.

  12.    This program is distributed in the hope that it will be useful,
  13.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.    GNU General Public License for more details.

  17.    You should have received a copy of the GNU General Public License
  18.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  20. #include "defs.h"
  21. #include "frame.h"
  22. #include "frame-unwind.h"
  23. #include "frame-base.h"
  24. #include "symtab.h"
  25. #include "gdbtypes.h"
  26. #include "gdbcmd.h"
  27. #include "gdbcore.h"
  28. #include "value.h"
  29. #include "inferior.h"
  30. #include "symfile.h"
  31. #include "objfiles.h"
  32. #include "osabi.h"
  33. #include "language.h"
  34. #include "arch-utils.h"
  35. #include "regcache.h"
  36. #include "trad-frame.h"
  37. #include "dis-asm.h"
  38. #include "objfiles.h"

  40. #include "m32r-tdep.h"

  42. /* Local functions */

  44. extern void _initialize_m32r_tdep (void);

  46. static CORE_ADDR
  47. ‌m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  48. {
  49.   /* Align to the size of an instruction (so that they can safely be
  50.      pushed onto the stack.  */
  51.   return sp & ~3;
  52. }


  55. /* Breakpoints

  57.    The little endian mode of M32R is unique.  In most of architectures,
  58.    two 16-bit instructions, A and B, are placed as the following:

  60.    Big endian:
  61.    A0 A1 B0 B1

  63.    Little endian:
  64.    A1 A0 B1 B0

  66.    In M32R, they are placed like this:

  68.    Big endian:
  69.    A0 A1 B0 B1

  71.    Little endian:
  72.    B1 B0 A1 A0

  74.    This is because M32R always fetches instructions in 32-bit.

  76.    The following functions take care of this behavior.  */

  78. static int
  79. ‌m32r_memory_insert_breakpoint (struct gdbarch *gdbarch,
  80.                                struct bp_target_info *bp_tgt)
  81. {
  82.   CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address;
  83.   int val;
  84.   gdb_byte buf[4];
  85.   gdb_byte contents_cache[4];
  86.   gdb_byte bp_entry[] = { 0x10, 0xf1 };        /* dpt */

  88.   /* Save the memory contents.  */
  89.   val = target_read_memory (addr & 0xfffffffc, contents_cache, 4);
  90.   if (val != 0)
  91.     return val;                        /* return error */

  93.   memcpy (bp_tgt->shadow_contents, contents_cache, 4);
  94.   bp_tgt->placed_size = bp_tgt->shadow_len = 4;

  96.   /* Determine appropriate breakpoint contents and size for this address.  */
  97.   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
  98.     {
  99.       if ((addr & 3) == 0)
  100.         {
  101.           buf[0] = bp_entry[0];
  102.           buf[1] = bp_entry[1];
  103.           buf[2] = contents_cache[2] & 0x7f;
  104.           buf[3] = contents_cache[3];
  105.         }
  106.       else
  107.         {
  108.           buf[0] = contents_cache[0];
  109.           buf[1] = contents_cache[1];
  110.           buf[2] = bp_entry[0];
  111.           buf[3] = bp_entry[1];
  112.         }
  113.     }
  114.   else                                /* little-endian */
  115.     {
  116.       if ((addr & 3) == 0)
  117.         {
  118.           buf[0] = contents_cache[0];
  119.           buf[1] = contents_cache[1] & 0x7f;
  120.           buf[2] = bp_entry[1];
  121.           buf[3] = bp_entry[0];
  122.         }
  123.       else
  124.         {
  125.           buf[0] = bp_entry[1];
  126.           buf[1] = bp_entry[0];
  127.           buf[2] = contents_cache[2];
  128.           buf[3] = contents_cache[3];
  129.         }
  130.     }

  132.   /* Write the breakpoint.  */
  133.   val = target_write_memory (addr & 0xfffffffc, buf, 4);
  134.   return val;
  135. }

  137. static int
  138. ‌m32r_memory_remove_breakpoint (struct gdbarch *gdbarch,
  139.                                struct bp_target_info *bp_tgt)
  140. {
  141.   CORE_ADDR addr = bp_tgt->placed_address;
  142.   int val;
  143.   gdb_byte buf[4];
  144.   gdb_byte *contents_cache = bp_tgt->shadow_contents;

  146.   buf[0] = contents_cache[0];
  147.   buf[1] = contents_cache[1];
  148.   buf[2] = contents_cache[2];
  149.   buf[3] = contents_cache[3];

  151.   /* Remove parallel bit.  */
  152.   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
  153.     {
  154.       if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0)
  155.         buf[2] &= 0x7f;
  156.     }
  157.   else                                /* little-endian */
  158.     {
  159.       if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0)
  160.         buf[1] &= 0x7f;
  161.     }

  163.   /* Write contents.  */
  164.   val = target_write_raw_memory (addr & 0xfffffffc, buf, 4);
  165.   return val;
  166. }

  168. static const gdb_byte *
  169. ‌m32r_breakpoint_from_pc (struct gdbarch *gdbarch,
  170.                          CORE_ADDR *pcptr, int *lenptr)
  171. {
  172.   static gdb_byte be_bp_entry[] = {
  173.     0x10, 0xf1, 0x70, 0x00
  174.   };        /* dpt -> nop */
  175.   static gdb_byte le_bp_entry[] = {
  176.     0x00, 0x70, 0xf1, 0x10
  177.   };        /* dpt -> nop */
  178.   gdb_byte *bp;

  180.   /* Determine appropriate breakpoint.  */
  181.   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
  182.     {
  183.       if ((*pcptr & 3) == 0)
  184.         {
  185.           bp = be_bp_entry;
  186.           *lenptr = 4;
  187.         }
  188.       else
  189.         {
  190.           bp = be_bp_entry;
  191.           *lenptr = 2;
  192.         }
  193.     }
  194.   else
  195.     {
  196.       if ((*pcptr & 3) == 0)
  197.         {
  198.           bp = le_bp_entry;
  199.           *lenptr = 4;
  200.         }
  201.       else
  202.         {
  203.           bp = le_bp_entry + 2;
  204.           *lenptr = 2;
  205.         }
  206.     }

  208.   return bp;
  209. }


  212. ‌char *m32r_register_names[] = {
  213.   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  214.   "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",
  215.   "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch",
  216.   "evb"
  217. };

  219. static const char *
  220. ‌m32r_register_name (struct gdbarch *gdbarch, int reg_nr)
  221. {
  222.   if (reg_nr < 0)
  223.     return NULL;
  224.   if (reg_nr >= M32R_NUM_REGS)
  225.     return NULL;
  226.   return m32r_register_names[reg_nr];
  227. }


  230. /* Return the GDB type object for the "standard" data type
  231.    of data in register N.  */

  233. static struct type *
  234. ‌m32r_register_type (struct gdbarch *gdbarch, int reg_nr)
  235. {
  236.   if (reg_nr == M32R_PC_REGNUM)
  237.     return builtin_type (gdbarch)->builtin_func_ptr;
  238.   else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM)
  239.     return builtin_type (gdbarch)->builtin_data_ptr;
  240.   else
  241.     return builtin_type (gdbarch)->builtin_int32;
  242. }


  245. /* Write into appropriate registers a function return value
  246.    of type TYPE, given in virtual format.

  248.    Things always get returned in RET1_REGNUM, RET2_REGNUM.  */

  250. static void
  251. ‌m32r_store_return_value (struct type *type, struct regcache *regcache,
  252.                          const void *valbuf)
  253. {
  254.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  255.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  256.   CORE_ADDR regval;
  257.   int len = TYPE_LENGTH (type);

  259.   regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order);
  260.   regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval);

  262.   if (len > 4)
  263.     {
  264.       regval = extract_unsigned_integer ((gdb_byte *) valbuf + 4,
  265.                                          len - 4, byte_order);
  266.       regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval);
  267.     }
  268. }

  270. /* This is required by skip_prologue.  The results of decoding a prologue
  271.    should be cached because this thrashing is getting nuts.  */

  273. static int
  274. ‌decode_prologue (struct gdbarch *gdbarch,
  275.                  CORE_ADDR start_pc, CORE_ADDR scan_limit,
  276.                  CORE_ADDR *pl_endptr, unsigned long *framelength)
  277. {
  278.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  279.   unsigned long framesize;
  280.   int insn;
  281.   int op1;
  282.   CORE_ADDR after_prologue = 0;
  283.   CORE_ADDR after_push = 0;
  284.   CORE_ADDR after_stack_adjust = 0;
  285.   CORE_ADDR current_pc;
  286.   LONGEST return_value;

  288.   framesize = 0;
  289.   after_prologue = 0;

  291.   for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2)
  292.     {
  293.       /* Check if current pc's location is readable.  */
  294.       if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value))
  295.         return -1;

  297.       insn = read_memory_unsigned_integer (current_pc, 2, byte_order);

  299.       if (insn == 0x0000)
  300.         break;

  302.       /* If this is a 32 bit instruction, we dont want to examine its
  303.          immediate data as though it were an instruction.  */
  304.       if (current_pc & 0x02)
  305.         {
  306.           /* Decode this instruction further.  */
  307.           insn &= 0x7fff;
  308.         }
  309.       else
  310.         {
  311.           if (insn & 0x8000)
  312.             {
  313.               if (current_pc == scan_limit)
  314.                 scan_limit += 2;        /* extend the search */

  316.               current_pc += 2;        /* skip the immediate data */

  318.               /* Check if current pc's location is readable.  */
  319.               if (!safe_read_memory_integer (current_pc, 2, byte_order,
  320.                                              &return_value))
  321.                 return -1;

  323.               if (insn == 0x8faf)        /* add3 sp, sp, xxxx */
  324.                 /* add 16 bit sign-extended offset */
  325.                 {
  326.                   framesize +=
  327.                     -((short) read_memory_unsigned_integer (current_pc,
  328.                                                             2, byte_order));
  329.                 }
  330.               else
  331.                 {
  332.                   if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */
  333.                       && safe_read_memory_integer (current_pc + 2,
  334.                                                    2, byte_order,
  335.                                                    &return_value)
  336.                       && read_memory_unsigned_integer (current_pc + 2,
  337.                                                        2, byte_order)
  338.                          == 0x0f24)
  339.                     {
  340.                       /* Subtract 24 bit sign-extended negative-offset.  */
  341.                       insn = read_memory_unsigned_integer (current_pc - 2,
  342.                                                            4, byte_order);
  343.                       if (insn & 0x00800000)        /* sign extend */
  344.                         insn |= 0xff000000;        /* negative */
  345.                       else
  346.                         insn &= 0x00ffffff;        /* positive */
  347.                       framesize += insn;
  348.                     }
  349.                 }
  350.               after_push = current_pc + 2;
  351.               continue;
  352.             }
  353.         }
  354.       op1 = insn & 0xf000;        /* Isolate just the first nibble.  */

  356.       if ((insn & 0xf0ff) == 0x207f)
  357.         {                        /* st reg, @-sp */
  358.           int regno;
  359.           framesize += 4;
  360.           regno = ((insn >> 8) & 0xf);
  361.           after_prologue = 0;
  362.           continue;
  363.         }
  364.       if ((insn >> 8) == 0x4f)        /* addi sp, xx */
  365.         /* Add 8 bit sign-extended offset.  */
  366.         {
  367.           int stack_adjust = (signed char) (insn & 0xff);

  369.           /* there are probably two of these stack adjustments:
  370.              1) A negative one in the prologue, and
  371.              2) A positive one in the epilogue.
  372.              We are only interested in the first one.  */

  374.           if (stack_adjust < 0)
  375.             {
  376.               framesize -= stack_adjust;
  377.               after_prologue = 0;
  378.               /* A frameless function may have no "mv fp, sp".
  379.                  In that case, this is the end of the prologue.  */
  380.               after_stack_adjust = current_pc + 2;
  381.             }
  382.           continue;
  383.         }
  384.       if (insn == 0x1d8f)
  385.         {                        /* mv fp, sp */
  386.           after_prologue = current_pc + 2;
  387.           break;                /* end of stack adjustments */
  388.         }

  390.       /* Nop looks like a branch, continue explicitly.  */
  391.       if (insn == 0x7000)
  392.         {
  393.           after_prologue = current_pc + 2;
  394.           continue;                /* nop occurs between pushes.  */
  395.         }
  396.       /* End of prolog if any of these are trap instructions.  */
  397.       if ((insn & 0xfff0) == 0x10f0)
  398.         {
  399.           after_prologue = current_pc;
  400.           break;
  401.         }
  402.       /* End of prolog if any of these are branch instructions.  */
  403.       if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000))
  404.         {
  405.           after_prologue = current_pc;
  406.           continue;
  407.         }
  408.       /* Some of the branch instructions are mixed with other types.  */
  409.       if (op1 == 0x1000)
  410.         {
  411.           int subop = insn & 0x0ff0;
  412.           if ((subop == 0x0ec0) || (subop == 0x0fc0))
  413.             {
  414.               after_prologue = current_pc;
  415.               continue;                /* jmp , jl */
  416.             }
  417.         }
  418.     }

  420.   if (framelength)
  421.     *framelength = framesize;

  423.   if (current_pc >= scan_limit)
  424.     {
  425.       if (pl_endptr)
  426.         {
  427.           if (after_stack_adjust != 0)
  428.             /* We did not find a "mv fp,sp", but we DID find
  429.                a stack_adjust.  Is it safe to use that as the
  430.                end of the prologue?  I just don't know.  */
  431.             {
  432.               *pl_endptr = after_stack_adjust;
  433.             }
  434.           else if (after_push != 0)
  435.             /* We did not find a "mv fp,sp", but we DID find
  436.                a push.  Is it safe to use that as the
  437.                end of the prologue?  I just don't know.  */
  438.             {
  439.               *pl_endptr = after_push;
  440.             }
  441.           else
  442.             /* We reached the end of the loop without finding the end
  443.                of the prologue.  No way to win -- we should report
  444.                failure.  The way we do that is to return the original
  445.                start_pc.  GDB will set a breakpoint at the start of
  446.                the function (etc.)  */
  447.             *pl_endptr = start_pc;
  448.         }
  449.       return 0;
  450.     }

  452.   if (after_prologue == 0)
  453.     after_prologue = current_pc;

  455.   if (pl_endptr)
  456.     *pl_endptr = after_prologue;

  458.   return 0;
  459. }                                /*  decode_prologue */

  461. /* Function: skip_prologue
  462.    Find end of function prologue.  */

  464. ‌#define DEFAULT_SEARCH_LIMIT 128

  466. static CORE_ADDR
  467. ‌m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  468. {
  469.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  470.   CORE_ADDR func_addr, func_end;
  471.   struct symtab_and_line sal;
  472.   LONGEST return_value;

  474.   /* See what the symbol table says.  */

  476.   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
  477.     {
  478.       sal = find_pc_line (func_addr, 0);

  480.       if (sal.line != 0 && sal.end <= func_end)
  481.         {
  482.           func_end = sal.end;
  483.         }
  484.       else
  485.         /* Either there's no line info, or the line after the prologue is after
  486.            the end of the function.  In this case, there probably isn't a
  487.            prologue.  */
  488.         {
  489.           func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT);
  490.         }
  491.     }
  492.   else
  493.     func_end = pc + DEFAULT_SEARCH_LIMIT;

  495.   /* If pc's location is not readable, just quit.  */
  496.   if (!safe_read_memory_integer (pc, 4, byte_order, &return_value))
  497.     return pc;

  499.   /* Find the end of prologue.  */
  500.   if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0)
  501.     return pc;

  503.   return sal.end;
  504. }

  506. ‌struct m32r_unwind_cache
  507. {
  508.   /* The previous frame's inner most stack address.  Used as this
  509.      frame ID's stack_addr.  */
  510.   CORE_ADDR prev_sp;
  511.   /* The frame's base, optionally used by the high-level debug info.  */
  512.   CORE_ADDR base;
  513.   int size;
  514.   /* How far the SP and r13 (FP) have been offset from the start of
  515.      the stack frame (as defined by the previous frame's stack
  516.      pointer).  */
  517.   LONGEST sp_offset;
  518.   LONGEST r13_offset;
  519.   int uses_frame;
  520.   /* Table indicating the location of each and every register.  */
  521.   struct trad_frame_saved_reg *saved_regs;
  522. };

  524. /* Put here the code to store, into fi->saved_regs, the addresses of
  525.    the saved registers of frame described by FRAME_INFO.  This
  526.    includes special registers such as pc and fp saved in special ways
  527.    in the stack frame.  sp is even more special: the address we return
  528.    for it IS the sp for the next frame.  */

  530. static struct m32r_unwind_cache *
  531. ‌m32r_frame_unwind_cache (struct frame_info *this_frame,
  532.                          void **this_prologue_cache)
  533. {
  534.   CORE_ADDR pc, scan_limit;
  535.   ULONGEST prev_sp;
  536.   ULONGEST this_base;
  537.   unsigned long op;
  538.   int i;
  539.   struct m32r_unwind_cache *info;


  542.   if ((*this_prologue_cache))
  543.     return (*this_prologue_cache);

  545.   info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache);
  546.   (*this_prologue_cache) = info;
  547.   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);

  549.   info->size = 0;
  550.   info->sp_offset = 0;
  551.   info->uses_frame = 0;

  553.   scan_limit = get_frame_pc (this_frame);
  554.   for (pc = get_frame_func (this_frame);
  555.        pc > 0 && pc < scan_limit; pc += 2)
  556.     {
  557.       if ((pc & 2) == 0)
  558.         {
  559.           op = get_frame_memory_unsigned (this_frame, pc, 4);
  560.           if ((op & 0x80000000) == 0x80000000)
  561.             {
  562.               /* 32-bit instruction */
  563.               if ((op & 0xffff0000) == 0x8faf0000)
  564.                 {
  565.                   /* add3 sp,sp,xxxx */
  566.                   short n = op & 0xffff;
  567.                   info->sp_offset += n;
  568.                 }
  569.               else if (((op >> 8) == 0xe4)
  570.                        && get_frame_memory_unsigned (this_frame, pc + 2,
  571.                                                      2) == 0x0f24)
  572.                 {
  573.                   /* ld24 r4, xxxxxx; sub sp, r4 */
  574.                   unsigned long n = op & 0xffffff;
  575.                   info->sp_offset += n;
  576.                   pc += 2;        /* skip sub instruction */
  577.                 }

  579.               if (pc == scan_limit)
  580.                 scan_limit += 2;        /* extend the search */
  581.               pc += 2;                /* skip the immediate data */
  582.               continue;
  583.             }
  584.         }

  586.       /* 16-bit instructions */
  587.       op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff;
  588.       if ((op & 0xf0ff) == 0x207f)
  589.         {
  590.           /* st rn, @-sp */
  591.           int regno = ((op >> 8) & 0xf);
  592.           info->sp_offset -= 4;
  593.           info->saved_regs[regno].addr = info->sp_offset;
  594.         }
  595.       else if ((op & 0xff00) == 0x4f00)
  596.         {
  597.           /* addi sp, xx */
  598.           int n = (signed char) (op & 0xff);
  599.           info->sp_offset += n;
  600.         }
  601.       else if (op == 0x1d8f)
  602.         {
  603.           /* mv fp, sp */
  604.           info->uses_frame = 1;
  605.           info->r13_offset = info->sp_offset;
  606.           break;                /* end of stack adjustments */
  607.         }
  608.       else if ((op & 0xfff0) == 0x10f0)
  609.         {
  610.           /* End of prologue if this is a trap instruction.  */
  611.           break;                /* End of stack adjustments.  */
  612.         }
  613.     }

  615.   info->size = -info->sp_offset;

  617.   /* Compute the previous frame's stack pointer (which is also the
  618.      frame's ID's stack address), and this frame's base pointer.  */
  619.   if (info->uses_frame)
  620.     {
  621.       /* The SP was moved to the FP.  This indicates that a new frame
  622.          was created.  Get THIS frame's FP value by unwinding it from
  623.          the next frame.  */
  624.       this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM);
  625.       /* The FP points at the last saved register.  Adjust the FP back
  626.          to before the first saved register giving the SP.  */
  627.       prev_sp = this_base + info->size;
  628.     }
  629.   else
  630.     {
  631.       /* Assume that the FP is this frame's SP but with that pushed
  632.          stack space added back.  */
  633.       this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM);
  634.       prev_sp = this_base + info->size;
  635.     }

  637.   /* Convert that SP/BASE into real addresses.  */
  638.   info->prev_sp = prev_sp;
  639.   info->base = this_base;

  641.   /* Adjust all the saved registers so that they contain addresses and
  642.      not offsets.  */
  643.   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
  644.     if (trad_frame_addr_p (info->saved_regs, i))
  645.       info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr);

  647.   /* The call instruction moves the caller's PC in the callee's LR.
  648.      Since this is an unwind, do the reverse.  Copy the location of LR
  649.      into PC (the address / regnum) so that a request for PC will be
  650.      converted into a request for the LR.  */
  651.   info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM];

  653.   /* The previous frame's SP needed to be computed.  Save the computed
  654.      value.  */
  655.   trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp);

  657.   return info;
  658. }

  660. static CORE_ADDR
  661. ‌m32r_read_pc (struct regcache *regcache)
  662. {
  663.   ULONGEST pc;
  664.   regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc);
  665.   return pc;
  666. }

  668. static CORE_ADDR
  669. ‌m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
  670. {
  671.   return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM);
  672. }


  675. static CORE_ADDR
  676. ‌m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
  677.                       struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
  678.                       struct value **args, CORE_ADDR sp, int struct_return,
  679.                       CORE_ADDR struct_addr)
  680. {
  681.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  682.   int stack_offset, stack_alloc;
  683.   int argreg = ARG1_REGNUM;
  684.   int argnum;
  685.   struct type *type;
  686.   enum type_code typecode;
  687.   CORE_ADDR regval;
  688.   gdb_byte *val;
  689.   gdb_byte valbuf[MAX_REGISTER_SIZE];
  690.   int len;

  692.   /* First force sp to a 4-byte alignment.  */
  693.   sp = sp & ~3;

  695.   /* Set the return address.  For the m32r, the return breakpoint is
  696.      always at BP_ADDR.  */
  697.   regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr);

  699.   /* If STRUCT_RETURN is true, then the struct return address (in
  700.      STRUCT_ADDR) will consume the first argument-passing register.
  701.      Both adjust the register count and store that value.  */
  702.   if (struct_return)
  703.     {
  704.       regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
  705.       argreg++;
  706.     }

  708.   /* Now make sure there's space on the stack.  */
  709.   for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
  710.     stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
  711.   sp -= stack_alloc;                /* Make room on stack for args.  */

  713.   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
  714.     {
  715.       type = value_type (args[argnum]);
  716.       typecode = TYPE_CODE (type);
  717.       len = TYPE_LENGTH (type);

  719.       memset (valbuf, 0, sizeof (valbuf));

  721.       /* Passes structures that do not fit in 2 registers by reference.  */
  722.       if (len > 8
  723.           && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
  724.         {
  725.           store_unsigned_integer (valbuf, 4, byte_order,
  726.                                   value_address (args[argnum]));
  727.           typecode = TYPE_CODE_PTR;
  728.           len = 4;
  729.           val = valbuf;
  730.         }
  731.       else if (len < 4)
  732.         {
  733.           /* Value gets right-justified in the register or stack word.  */
  734.           memcpy (valbuf + (register_size (gdbarch, argreg) - len),
  735.                   (gdb_byte *) value_contents (args[argnum]), len);
  736.           val = valbuf;
  737.         }
  738.       else
  739.         val = (gdb_byte *) value_contents (args[argnum]);

  741.       while (len > 0)
  742.         {
  743.           if (argreg > ARGN_REGNUM)
  744.             {
  745.               /* Must go on the stack.  */
  746.               write_memory (sp + stack_offset, val, 4);
  747.               stack_offset += 4;
  748.             }
  749.           else if (argreg <= ARGN_REGNUM)
  750.             {
  751.               /* There's room in a register.  */
  752.               regval =
  753.                 extract_unsigned_integer (val,
  754.                                           register_size (gdbarch, argreg),
  755.                                           byte_order);
  756.               regcache_cooked_write_unsigned (regcache, argreg++, regval);
  757.             }

  759.           /* Store the value 4 bytes at a time.  This means that things
  760.              larger than 4 bytes may go partly in registers and partly
  761.              on the stack.  */
  762.           len -= register_size (gdbarch, argreg);
  763.           val += register_size (gdbarch, argreg);
  764.         }
  765.     }

  767.   /* Finally, update the SP register.  */
  768.   regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp);

  770.   return sp;
  771. }


  774. /* Given a return value in `regbuf' with a type `valtype',
  775.    extract and copy its value into `valbuf'.  */

  777. static void
  778. ‌m32r_extract_return_value (struct type *type, struct regcache *regcache,
  779.                            void *dst)
  780. {
  781.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  782.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  783.   bfd_byte *valbuf = dst;
  784.   int len = TYPE_LENGTH (type);
  785.   ULONGEST tmp;

  787.   /* By using store_unsigned_integer we avoid having to do
  788.      anything special for small big-endian values.  */
  789.   regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp);
  790.   store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), byte_order, tmp);

  792.   /* Ignore return values more than 8 bytes in size because the m32r
  793.      returns anything more than 8 bytes in the stack.  */
  794.   if (len > 4)
  795.     {
  796.       regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp);
  797.       store_unsigned_integer (valbuf + len - 4, 4, byte_order, tmp);
  798.     }
  799. }

  801. static enum return_value_convention
  802. ‌m32r_return_value (struct gdbarch *gdbarch, struct value *function,
  803.                    struct type *valtype, struct regcache *regcache,
  804.                    gdb_byte *readbuf, const gdb_byte *writebuf)
  805. {
  806.   if (TYPE_LENGTH (valtype) > 8)
  807.     return RETURN_VALUE_STRUCT_CONVENTION;
  808.   else
  809.     {
  810.       if (readbuf != NULL)
  811.         m32r_extract_return_value (valtype, regcache, readbuf);
  812.       if (writebuf != NULL)
  813.         m32r_store_return_value (valtype, regcache, writebuf);
  814.       return RETURN_VALUE_REGISTER_CONVENTION;
  815.     }
  816. }



  820. static CORE_ADDR
  821. ‌m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
  822. {
  823.   return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM);
  824. }

  826. /* Given a GDB frame, determine the address of the calling function's
  827.    frame.  This will be used to create a new GDB frame struct.  */

  829. static void
  830. ‌m32r_frame_this_id (struct frame_info *this_frame,
  831.                     void **this_prologue_cache, struct frame_id *this_id)
  832. {
  833.   struct m32r_unwind_cache *info
  834.     = m32r_frame_unwind_cache (this_frame, this_prologue_cache);
  835.   CORE_ADDR base;
  836.   CORE_ADDR func;
  837.   struct bound_minimal_symbol msym_stack;
  838.   struct frame_id id;

  840.   /* The FUNC is easy.  */
  841.   func = get_frame_func (this_frame);

  843.   /* Check if the stack is empty.  */
  844.   msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
  845.   if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack))
  846.     return;

  848.   /* Hopefully the prologue analysis either correctly determined the
  849.      frame's base (which is the SP from the previous frame), or set
  850.      that base to "NULL".  */
  851.   base = info->prev_sp;
  852.   if (base == 0)
  853.     return;

  855.   id = frame_id_build (base, func);
  856.   (*this_id) = id;
  857. }

  859. static struct value *
  860. ‌m32r_frame_prev_register (struct frame_info *this_frame,
  861.                           void **this_prologue_cache, int regnum)
  862. {
  863.   struct m32r_unwind_cache *info
  864.     = m32r_frame_unwind_cache (this_frame, this_prologue_cache);
  865.   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
  866. }

  868. ‌static const struct frame_unwind m32r_frame_unwind = {
  869.   NORMAL_FRAME,
  870.   default_frame_unwind_stop_reason,
  871.   m32r_frame_this_id,
  872.   m32r_frame_prev_register,
  873.   NULL,
  874.   default_frame_sniffer
  875. };

  877. static CORE_ADDR
  878. ‌m32r_frame_base_address (struct frame_info *this_frame, void **this_cache)
  879. {
  880.   struct m32r_unwind_cache *info
  881.     = m32r_frame_unwind_cache (this_frame, this_cache);
  882.   return info->base;
  883. }

  885. ‌static const struct frame_base m32r_frame_base = {
  886.   &m32r_frame_unwind,
  887.   m32r_frame_base_address,
  888.   m32r_frame_base_address,
  889.   m32r_frame_base_address
  890. };

  892. /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
  893.    frame.  The frame ID's base needs to match the TOS value saved by
  894.    save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint.  */

  896. static struct frame_id
  897. ‌m32r_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
  898. {
  899.   CORE_ADDR sp = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM);
  900.   return frame_id_build (sp, get_frame_pc (this_frame));
  901. }


  904. ‌static gdbarch_init_ftype m32r_gdbarch_init;

  906. static struct gdbarch *
  907. ‌m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
  908. {
  909.   struct gdbarch *gdbarch;
  910.   struct gdbarch_tdep *tdep;

  912.   /* If there is already a candidate, use it.  */
  913.   arches = gdbarch_list_lookup_by_info (arches, &info);
  914.   if (arches != NULL)
  915.     return arches->gdbarch;

  917.   /* Allocate space for the new architecture.  */
  918.   tdep = XNEW (struct gdbarch_tdep);
  919.   gdbarch = gdbarch_alloc (&info, tdep);

  921.   set_gdbarch_read_pc (gdbarch, m32r_read_pc);
  922.   set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp);

  924.   set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS);
  925.   set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM);
  926.   set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM);
  927.   set_gdbarch_register_name (gdbarch, m32r_register_name);
  928.   set_gdbarch_register_type (gdbarch, m32r_register_type);

  930.   set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call);
  931.   set_gdbarch_return_value (gdbarch, m32r_return_value);

  933.   set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue);
  934.   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
  935.   set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc);
  936.   set_gdbarch_memory_insert_breakpoint (gdbarch,
  937.                                         m32r_memory_insert_breakpoint);
  938.   set_gdbarch_memory_remove_breakpoint (gdbarch,
  939.                                         m32r_memory_remove_breakpoint);

  941.   set_gdbarch_frame_align (gdbarch, m32r_frame_align);

  943.   frame_base_set_default (gdbarch, &m32r_frame_base);

  945.   /* Methods for saving / extracting a dummy frame's ID.  The ID's
  946.      stack address must match the SP value returned by
  947.      PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos.  */
  948.   set_gdbarch_dummy_id (gdbarch, m32r_dummy_id);

  950.   /* Return the unwound PC value.  */
  951.   set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc);

  953.   set_gdbarch_print_insn (gdbarch, print_insn_m32r);

  955.   /* Hook in ABI-specific overrides, if they have been registered.  */
  956.   gdbarch_init_osabi (info, gdbarch);

  958.   /* Hook in the default unwinders.  */
  959.   frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind);

  961.   /* Support simple overlay manager.  */
  962.   set_gdbarch_overlay_update (gdbarch, simple_overlay_update);

  964.   return gdbarch;
  965. }

  967. void
  968. ‌_initialize_m32r_tdep (void)
  969. {
  970.   register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init);
  971. }