gdb/aarch64-linux-nat.c - gdb

Global variables defined

Data types defined

Functions defined

Macros defined

Source code

  1. /* Native-dependent code for GNU/Linux AArch64.

  3.    Copyright (C) 2011-2015 Free Software Foundation, Inc.
  4.    Contributed by ARM Ltd.

  6.    This file is part of GDB.

  8.    This program is free software; you can redistribute it and/or modify
  9.    it under the terms of the GNU General Public License as published by
  10.    the Free Software Foundation; either version 3 of the License, or
  11.    (at your option) any later version.

  13.    This program is distributed in the hope that it will be useful,
  14.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16.    GNU General Public License for more details.

  18.    You should have received a copy of the GNU General Public License
  19.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  21. #include "defs.h"

  23. #include "inferior.h"
  24. #include "gdbcore.h"
  25. #include "regcache.h"
  26. #include "linux-nat.h"
  27. #include "target-descriptions.h"
  28. #include "auxv.h"
  29. #include "gdbcmd.h"
  30. #include "aarch64-tdep.h"
  31. #include "aarch64-linux-tdep.h"
  32. #include "elf/common.h"

  34. #include <sys/ptrace.h>
  35. #include <sys/utsname.h>
  36. #include <asm/ptrace.h>

  38. #include "gregset.h"

  40. #include "features/aarch64.c"

  42. /* Defines ps_err_e, struct ps_prochandle.  */
  43. #include "gdb_proc_service.h"

  45. #ifndef TRAP_HWBKPT
  46. ‌#define TRAP_HWBKPT 0x0004
  47. #endif

  49. /* On GNU/Linux, threads are implemented as pseudo-processes, in which
  50.    case we may be tracing more than one process at a time.  In that
  51.    case, inferior_ptid will contain the main process ID and the
  52.    individual thread (process) ID.  get_thread_id () is used to get
  53.    the thread id if it's available, and the process id otherwise.  */

  55. static int
  56. ‌get_thread_id (ptid_t ptid)
  57. {
  58.   int tid = ptid_get_lwp (ptid);

  60.   if (0 == tid)
  61.     tid = ptid_get_pid (ptid);
  62.   return tid;
  63. }

  65. /* Macro definitions, data structures, and code for the hardware
  66.    breakpoint and hardware watchpoint support follow.  We use the
  67.    following abbreviations throughout the code:

  69.    hw - hardware
  70.    bp - breakpoint
  71.    wp - watchpoint  */

  73. /* Maximum number of hardware breakpoint and watchpoint registers.
  74.    Neither of these values may exceed the width of dr_changed_t
  75.    measured in bits.  */

  77. ‌#define AARCH64_HBP_MAX_NUM 16
  78. ‌#define AARCH64_HWP_MAX_NUM 16

  80. /* Alignment requirement in bytes for addresses written to
  81.    hardware breakpoint and watchpoint value registers.

  83.    A ptrace call attempting to set an address that does not meet the
  84.    alignment criteria will fail.  Limited support has been provided in
  85.    this port for unaligned watchpoints, such that from a GDB user
  86.    perspective, an unaligned watchpoint may be requested.

  88.    This is achieved by minimally enlarging the watched area to meet the
  89.    alignment requirement, and if necessary, splitting the watchpoint
  90.    over several hardware watchpoint registers.  */

  92. ‌#define AARCH64_HBP_ALIGNMENT 4
  93. ‌#define AARCH64_HWP_ALIGNMENT 8

  95. /* The maximum length of a memory region that can be watched by one
  96.    hardware watchpoint register.  */

  98. ‌#define AARCH64_HWP_MAX_LEN_PER_REG 8

  100. /* ptrace hardware breakpoint resource info is formatted as follows:

  102.    31             24             16               8              0
  103.    +---------------+--------------+---------------+---------------+
  104.    |   RESERVED    |   RESERVED   |   DEBUG_ARCH  |  NUM_SLOTS    |
  105.    +---------------+--------------+---------------+---------------+  */


  108. /* Macros to extract fields from the hardware debug information word.  */
  109. ‌#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
  110. ‌#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)

  112. /* Macro for the expected version of the ARMv8-A debug architecture.  */
  113. ‌#define AARCH64_DEBUG_ARCH_V8 0x6

  115. /* Number of hardware breakpoints/watchpoints the target supports.
  116.    They are initialized with values obtained via the ptrace calls
  117.    with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively.  */

  119. ‌static int aarch64_num_bp_regs;
  120. ‌static int aarch64_num_wp_regs;

  122. /* Each bit of a variable of this type is used to indicate whether a
  123.    hardware breakpoint or watchpoint setting has been changed since
  124.    the last update.

  126.    Bit N corresponds to the Nth hardware breakpoint or watchpoint
  127.    setting which is managed in aarch64_debug_reg_state, where N is
  128.    valid between 0 and the total number of the hardware breakpoint or
  129.    watchpoint debug registers minus 1.

  131.    When bit N is 1, the corresponding breakpoint or watchpoint setting
  132.    has changed, and therefore the corresponding hardware debug
  133.    register needs to be updated via the ptrace interface.

  135.    In the per-thread arch-specific data area, we define two such
  136.    variables for per-thread hardware breakpoint and watchpoint
  137.    settings respectively.

  139.    This type is part of the mechanism which helps reduce the number of
  140.    ptrace calls to the kernel, i.e. avoid asking the kernel to write
  141.    to the debug registers with unchanged values.  */

  143. ‌typedef ULONGEST dr_changed_t;

  145. /* Set each of the lower M bits of X to 1; assert X is wide enough.  */

  147. ‌#define DR_MARK_ALL_CHANGED(x, m)                                        \
  148.   do                                                                        \
  149.     {                                                                        \
  150.       gdb_assert (sizeof ((x)) * 8 >= (m));                                \
  151.       (x) = (((dr_changed_t)1 << (m)) - 1);                                \
  152.     } while (0)

  154. ‌#define DR_MARK_N_CHANGED(x, n)                                                \
  155.   do                                                                        \
  156.     {                                                                        \
  157.       (x) |= ((dr_changed_t)1 << (n));                                        \
  158.     } while (0)

  160. ‌#define DR_CLEAR_CHANGED(x)                                                \
  161.   do                                                                        \
  162.     {                                                                        \
  163.       (x) = 0;                                                                \
  164.     } while (0)

  166. ‌#define DR_HAS_CHANGED(x) ((x) != 0)
  167. ‌#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))

  169. /* Structure for managing the hardware breakpoint/watchpoint resources.
  170.    DR_ADDR_* stores the address, DR_CTRL_* stores the control register
  171.    content, and DR_REF_COUNT_* counts the numbers of references to the
  172.    corresponding bp/wp, by which way the limited hardware resources
  173.    are not wasted on duplicated bp/wp settings (though so far gdb has
  174.    done a good job by not sending duplicated bp/wp requests).  */

  176. ‌struct aarch64_debug_reg_state
  177. {
  178.   /* hardware breakpoint */
  179.   CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
  180.   unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
  181.   unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];

  183.   /* hardware watchpoint */
  184.   CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
  185.   unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
  186.   unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
  187. };

  189. /* Per-process data.  We don't bind this to a per-inferior registry
  190.    because of targets like x86 GNU/Linux that need to keep track of
  191.    processes that aren't bound to any inferior (e.g., fork children,
  192.    checkpoints).  */

  194. ‌struct aarch64_process_info
  195. {
  196.   /* Linked list.  */
  197.   struct aarch64_process_info *next;

  199.   /* The process identifier.  */
  200.   pid_t pid;

  202.   /* Copy of aarch64 hardware debug registers.  */
  203.   struct aarch64_debug_reg_state state;
  204. };

  206. ‌static struct aarch64_process_info *aarch64_process_list = NULL;

  208. /* Find process data for process PID.  */

  210. static struct aarch64_process_info *
  211. ‌aarch64_find_process_pid (pid_t pid)
  212. {
  213.   struct aarch64_process_info *proc;

  215.   for (proc = aarch64_process_list; proc; proc = proc->next)
  216.     if (proc->pid == pid)
  217.       return proc;

  219.   return NULL;
  220. }

  222. /* Add process data for process PID.  Returns newly allocated info
  223.    object.  */

  225. static struct aarch64_process_info *
  226. ‌aarch64_add_process (pid_t pid)
  227. {
  228.   struct aarch64_process_info *proc;

  230.   proc = xcalloc (1, sizeof (*proc));
  231.   proc->pid = pid;

  233.   proc->next = aarch64_process_list;
  234.   aarch64_process_list = proc;

  236.   return proc;
  237. }

  239. /* Get data specific info for process PID, creating it if necessary.
  240.    Never returns NULL.  */

  242. static struct aarch64_process_info *
  243. ‌aarch64_process_info_get (pid_t pid)
  244. {
  245.   struct aarch64_process_info *proc;

  247.   proc = aarch64_find_process_pid (pid);
  248.   if (proc == NULL)
  249.     proc = aarch64_add_process (pid);

  251.   return proc;
  252. }

  254. /* Called whenever GDB is no longer debugging process PID.  It deletes
  255.    data structures that keep track of debug register state.  */

  257. static void
  258. ‌aarch64_forget_process (pid_t pid)
  259. {
  260.   struct aarch64_process_info *proc, **proc_link;

  262.   proc = aarch64_process_list;
  263.   proc_link = &aarch64_process_list;

  265.   while (proc != NULL)
  266.     {
  267.       if (proc->pid == pid)
  268.         {
  269.           *proc_link = proc->next;

  271.           xfree (proc);
  272.           return;
  273.         }

  275.       proc_link = &proc->next;
  276.       proc = *proc_link;
  277.     }
  278. }

  280. /* Get debug registers state for process PID.  */

  282. static struct aarch64_debug_reg_state *
  283. ‌aarch64_get_debug_reg_state (pid_t pid)
  284. {
  285.   return &aarch64_process_info_get (pid)->state;
  286. }

  288. /* Per-thread arch-specific data we want to keep.  */

  290. ‌struct arch_lwp_info
  291. {
  292.   /* When bit N is 1, it indicates the Nth hardware breakpoint or
  293.      watchpoint register pair needs to be updated when the thread is
  294.      resumed; see aarch64_linux_prepare_to_resume.  */
  295.   dr_changed_t dr_changed_bp;
  296.   dr_changed_t dr_changed_wp;
  297. };

  299. /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
  300.    registers with data from *STATE.  */

  302. static void
  303. ‌aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
  304.                               int tid, int watchpoint)
  305. {
  306.   int i, count;
  307.   struct iovec iov;
  308.   struct user_hwdebug_state regs;
  309.   const CORE_ADDR *addr;
  310.   const unsigned int *ctrl;

  312.   memset (&regs, 0, sizeof (regs));
  313.   iov.iov_base = &regs;
  314.   count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
  315.   addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
  316.   ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
  317.   if (count == 0)
  318.     return;
  319.   iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
  320.                  + sizeof (regs.dbg_regs [count - 1]));

  322.   for (i = 0; i < count; i++)
  323.     {
  324.       regs.dbg_regs[i].addr = addr[i];
  325.       regs.dbg_regs[i].ctrl = ctrl[i];
  326.     }

  328.   if (ptrace (PTRACE_SETREGSET, tid,
  329.               watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
  330.               (void *) &iov))
  331.     error (_("Unexpected error setting hardware debug registers"));
  332. }

  334. ‌struct aarch64_dr_update_callback_param
  335. {
  336.   int is_watchpoint;
  337.   unsigned int idx;
  338. };

  340. /* Callback for iterate_over_lwps.  Records the
  341.    information about the change of one hardware breakpoint/watchpoint
  342.    setting for the thread LWP.
  343.    The information is passed in via PTR.
  344.    N.B.  The actual updating of hardware debug registers is not
  345.    carried out until the moment the thread is resumed.  */

  347. static int
  348. ‌debug_reg_change_callback (struct lwp_info *lwp, void *ptr)
  349. {
  350.   struct aarch64_dr_update_callback_param *param_p
  351.     = (struct aarch64_dr_update_callback_param *) ptr;
  352.   int pid = get_thread_id (lwp->ptid);
  353.   int idx = param_p->idx;
  354.   int is_watchpoint = param_p->is_watchpoint;
  355.   struct arch_lwp_info *info = lwp->arch_private;
  356.   dr_changed_t *dr_changed_ptr;
  357.   dr_changed_t dr_changed;

  359.   if (info == NULL)
  360.     info = lwp->arch_private = XCNEW (struct arch_lwp_info);

  362.   if (show_debug_regs)
  363.     {
  364.       fprintf_unfiltered (gdb_stdlog,
  365.                           "debug_reg_change_callback: \n\tOn entry:\n");
  366.       fprintf_unfiltered (gdb_stdlog,
  367.                           "\tpid%d, dr_changed_bp=0x%s, "
  368.                           "dr_changed_wp=0x%s\n",
  369.                           pid, phex (info->dr_changed_bp, 8),
  370.                           phex (info->dr_changed_wp, 8));
  371.     }

  373.   dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp
  374.     : &info->dr_changed_bp;
  375.   dr_changed = *dr_changed_ptr;

  377.   gdb_assert (idx >= 0
  378.               && (idx <= (is_watchpoint ? aarch64_num_wp_regs
  379.                           : aarch64_num_bp_regs)));

  381.   /* The actual update is done later just before resuming the lwp,
  382.      we just mark that one register pair needs updating.  */
  383.   DR_MARK_N_CHANGED (dr_changed, idx);
  384.   *dr_changed_ptr = dr_changed;

  386.   /* If the lwp isn't stopped, force it to momentarily pause, so
  387.      we can update its debug registers.  */
  388.   if (!lwp->stopped)
  389.     linux_stop_lwp (lwp);

  391.   if (show_debug_regs)
  392.     {
  393.       fprintf_unfiltered (gdb_stdlog,
  394.                           "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, "
  395.                           "dr_changed_wp=0x%s\n",
  396.                           pid, phex (info->dr_changed_bp, 8),
  397.                           phex (info->dr_changed_wp, 8));
  398.     }

  400.   /* Continue the iteration.  */
  401.   return 0;
  402. }

  404. /* Notify each thread that their IDXth breakpoint/watchpoint register
  405.    pair needs to be updated.  The message will be recorded in each
  406.    thread's arch-specific data area, the actual updating will be done
  407.    when the thread is resumed.  */

  409. static void
  410. ‌aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
  411.                                  int is_watchpoint, unsigned int idx)
  412. {
  413.   struct aarch64_dr_update_callback_param param;
  414.   ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid));

  416.   param.is_watchpoint = is_watchpoint;
  417.   param.idx = idx;

  419.   iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) &param);
  420. }

  422. /* Print the values of the cached breakpoint/watchpoint registers.  */

  424. static void
  425. ‌aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
  426.                               const char *func, CORE_ADDR addr,
  427.                               int len, int type)
  428. {
  429.   int i;

  431.   fprintf_unfiltered (gdb_stdlog, "%s", func);
  432.   if (addr || len)
  433.     fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)",
  434.                         (unsigned long) addr, len,
  435.                         type == hw_write ? "hw-write-watchpoint"
  436.                         : (type == hw_read ? "hw-read-watchpoint"
  437.                            : (type == hw_access ? "hw-access-watchpoint"
  438.                               : (type == hw_execute ? "hw-breakpoint"
  439.                                  : "??unknown??"))));
  440.   fprintf_unfiltered (gdb_stdlog, ":\n");

  442.   fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n");
  443.   for (i = 0; i < aarch64_num_bp_regs; i++)
  444.     fprintf_unfiltered (gdb_stdlog,
  445.                         "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
  446.                         i, state->dr_addr_bp[i],
  447.                         state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);

  449.   fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n");
  450.   for (i = 0; i < aarch64_num_wp_regs; i++)
  451.     fprintf_unfiltered (gdb_stdlog,
  452.                         "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
  453.                         i, state->dr_addr_wp[i],
  454.                         state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
  455. }

  457. /* Fill GDB's register array with the general-purpose register values
  458.    from the current thread.  */

  460. static void
  461. ‌fetch_gregs_from_thread (struct regcache *regcache)
  462. {
  463.   int ret, regno, tid;
  464.   elf_gregset_t regs;
  465.   struct iovec iovec;

  467.   tid = get_thread_id (inferior_ptid);

  469.   iovec.iov_base = &regs;
  470.   iovec.iov_len = sizeof (regs);

  472.   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
  473.   if (ret < 0)
  474.     perror_with_name (_("Unable to fetch general registers."));

  476.   for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
  477.     regcache_raw_supply (regcache, regno,
  478.                          (char *) &regs[regno - AARCH64_X0_REGNUM]);
  479. }

  481. /* Store to the current thread the valid general-purpose register
  482.    values in the GDB's register array.  */

  484. static void
  485. ‌store_gregs_to_thread (const struct regcache *regcache)
  486. {
  487.   int ret, regno, tid;
  488.   elf_gregset_t regs;
  489.   struct iovec iovec;

  491.   tid = get_thread_id (inferior_ptid);

  493.   iovec.iov_base = &regs;
  494.   iovec.iov_len = sizeof (regs);

  496.   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
  497.   if (ret < 0)
  498.     perror_with_name (_("Unable to fetch general registers."));

  500.   for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
  501.     if (REG_VALID == regcache_register_status (regcache, regno))
  502.       regcache_raw_collect (regcache, regno,
  503.                             (char *) &regs[regno - AARCH64_X0_REGNUM]);

  505.   ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
  506.   if (ret < 0)
  507.     perror_with_name (_("Unable to store general registers."));
  508. }

  510. /* Fill GDB's register array with the fp/simd register values
  511.    from the current thread.  */

  513. static void
  514. ‌fetch_fpregs_from_thread (struct regcache *regcache)
  515. {
  516.   int ret, regno, tid;
  517.   elf_fpregset_t regs;
  518.   struct iovec iovec;

  520.   tid = get_thread_id (inferior_ptid);

  522.   iovec.iov_base = &regs;
  523.   iovec.iov_len = sizeof (regs);

  525.   ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
  526.   if (ret < 0)
  527.     perror_with_name (_("Unable to fetch FP/SIMD registers."));

  529.   for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
  530.     regcache_raw_supply (regcache, regno,
  531.                          (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);

  533.   regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
  534.   regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);
  535. }

  537. /* Store to the current thread the valid fp/simd register
  538.    values in the GDB's register array.  */

  540. static void
  541. ‌store_fpregs_to_thread (const struct regcache *regcache)
  542. {
  543.   int ret, regno, tid;
  544.   elf_fpregset_t regs;
  545.   struct iovec iovec;

  547.   tid = get_thread_id (inferior_ptid);

  549.   iovec.iov_base = &regs;
  550.   iovec.iov_len = sizeof (regs);

  552.   ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
  553.   if (ret < 0)
  554.     perror_with_name (_("Unable to fetch FP/SIMD registers."));

  556.   for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
  557.     if (REG_VALID == regcache_register_status (regcache, regno))
  558.       regcache_raw_collect (regcache, regno,
  559.                             (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);

  561.   if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM))
  562.     regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
  563.   if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM))
  564.     regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);

  566.   ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
  567.   if (ret < 0)
  568.     perror_with_name (_("Unable to store FP/SIMD registers."));
  569. }

  571. /* Implement the "to_fetch_register" target_ops method.  */

  573. static void
  574. ‌aarch64_linux_fetch_inferior_registers (struct target_ops *ops,
  575.                                         struct regcache *regcache,
  576.                                         int regno)
  577. {
  578.   if (regno == -1)
  579.     {
  580.       fetch_gregs_from_thread (regcache);
  581.       fetch_fpregs_from_thread (regcache);
  582.     }
  583.   else if (regno < AARCH64_V0_REGNUM)
  584.     fetch_gregs_from_thread (regcache);
  585.   else
  586.     fetch_fpregs_from_thread (regcache);
  587. }

  589. /* Implement the "to_store_register" target_ops method.  */

  591. static void
  592. ‌aarch64_linux_store_inferior_registers (struct target_ops *ops,
  593.                                         struct regcache *regcache,
  594.                                         int regno)
  595. {
  596.   if (regno == -1)
  597.     {
  598.       store_gregs_to_thread (regcache);
  599.       store_fpregs_to_thread (regcache);
  600.     }
  601.   else if (regno < AARCH64_V0_REGNUM)
  602.     store_gregs_to_thread (regcache);
  603.   else
  604.     store_fpregs_to_thread (regcache);
  605. }

  607. /* Fill register REGNO (if it is a general-purpose register) in
  608.    *GREGSETPS with the value in GDB's register array.  If REGNO is -1,
  609.    do this for all registers.  */

  611. void
  612. ‌fill_gregset (const struct regcache *regcache,
  613.               gdb_gregset_t *gregsetp, int regno)
  614. {
  615.   regcache_collect_regset (&aarch64_linux_gregset, regcache,
  616.                            regno, (gdb_byte *) gregsetp,
  617.                            AARCH64_LINUX_SIZEOF_GREGSET);
  618. }

  620. /* Fill GDB's register array with the general-purpose register values
  621.    in *GREGSETP.  */

  623. void
  624. ‌supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
  625. {
  626.   regcache_supply_regset (&aarch64_linux_gregset, regcache, -1,
  627.                           (const gdb_byte *) gregsetp,
  628.                           AARCH64_LINUX_SIZEOF_GREGSET);
  629. }

  631. /* Fill register REGNO (if it is a floating-point register) in
  632.    *FPREGSETP with the value in GDB's register array.  If REGNO is -1,
  633.    do this for all registers.  */

  635. void
  636. ‌fill_fpregset (const struct regcache *regcache,
  637.                gdb_fpregset_t *fpregsetp, int regno)
  638. {
  639.   regcache_collect_regset (&aarch64_linux_fpregset, regcache,
  640.                            regno, (gdb_byte *) fpregsetp,
  641.                            AARCH64_LINUX_SIZEOF_FPREGSET);
  642. }

  644. /* Fill GDB's register array with the floating-point register values
  645.    in *FPREGSETP.  */

  647. void
  648. ‌supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
  649. {
  650.   regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1,
  651.                           (const gdb_byte *) fpregsetp,
  652.                           AARCH64_LINUX_SIZEOF_FPREGSET);
  653. }

  655. /* Called when resuming a thread.
  656.    The hardware debug registers are updated when there is any change.  */

  658. static void
  659. ‌aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
  660. {
  661.   struct arch_lwp_info *info = lwp->arch_private;

  663.   /* NULL means this is the main thread still going through the shell,
  664.      or, no watchpoint has been set yet.  In that case, there's
  665.      nothing to do.  */
  666.   if (info == NULL)
  667.     return;

  669.   if (DR_HAS_CHANGED (info->dr_changed_bp)
  670.       || DR_HAS_CHANGED (info->dr_changed_wp))
  671.     {
  672.       int tid = ptid_get_lwp (lwp->ptid);
  673.       struct aarch64_debug_reg_state *state
  674.         = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid));

  676.       if (show_debug_regs)
  677.         fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid);

  679.       /* Watchpoints.  */
  680.       if (DR_HAS_CHANGED (info->dr_changed_wp))
  681.         {
  682.           aarch64_linux_set_debug_regs (state, tid, 1);
  683.           DR_CLEAR_CHANGED (info->dr_changed_wp);
  684.         }

  686.       /* Breakpoints.  */
  687.       if (DR_HAS_CHANGED (info->dr_changed_bp))
  688.         {
  689.           aarch64_linux_set_debug_regs (state, tid, 0);
  690.           DR_CLEAR_CHANGED (info->dr_changed_bp);
  691.         }
  692.     }
  693. }

  695. static void
  696. ‌aarch64_linux_new_thread (struct lwp_info *lp)
  697. {
  698.   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);

  700.   /* Mark that all the hardware breakpoint/watchpoint register pairs
  701.      for this thread need to be initialized.  */
  702.   DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs);
  703.   DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs);

  705.   lp->arch_private = info;
  706. }

  708. /* linux_nat_new_fork hook.   */

  710. static void
  711. ‌aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid)
  712. {
  713.   pid_t parent_pid;
  714.   struct aarch64_debug_reg_state *parent_state;
  715.   struct aarch64_debug_reg_state *child_state;

  717.   /* NULL means no watchpoint has ever been set in the parent.  In
  718.      that case, there's nothing to do.  */
  719.   if (parent->arch_private == NULL)
  720.     return;

  722.   /* GDB core assumes the child inherits the watchpoints/hw
  723.      breakpoints of the parent, and will remove them all from the
  724.      forked off process.  Copy the debug registers mirrors into the
  725.      new process so that all breakpoints and watchpoints can be
  726.      removed together.  */

  728.   parent_pid = ptid_get_pid (parent->ptid);
  729.   parent_state = aarch64_get_debug_reg_state (parent_pid);
  730.   child_state = aarch64_get_debug_reg_state (child_pid);
  731.   *child_state = *parent_state;
  732. }


  735. /* Called by libthread_db.  Returns a pointer to the thread local
  736.    storage (or its descriptor).  */

  738. ps_err_e
  739. ‌ps_get_thread_area (const struct ps_prochandle *ph,
  740.                     lwpid_t lwpid, int idx, void **base)
  741. {
  742.   struct iovec iovec;
  743.   uint64_t reg;

  745.   iovec.iov_base = &reg;
  746.   iovec.iov_len = sizeof (reg);

  748.   if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0)
  749.     return PS_ERR;

  751.   /* IDX is the bias from the thread pointer to the beginning of the
  752.      thread descriptor.  It has to be subtracted due to implementation
  753.      quirks in libthread_db.  */
  754.   *base = (void *) (reg - idx);

  756.   return PS_OK;
  757. }


  760. /* Get the hardware debug register capacity information.  */

  762. static void
  763. ‌aarch64_linux_get_debug_reg_capacity (void)
  764. {
  765.   int tid;
  766.   struct iovec iov;
  767.   struct user_hwdebug_state dreg_state;

  769.   tid = get_thread_id (inferior_ptid);
  770.   iov.iov_base = &dreg_state;
  771.   iov.iov_len = sizeof (dreg_state);

  773.   /* Get hardware watchpoint register info.  */
  774.   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
  775.       && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
  776.     {
  777.       aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
  778.       if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
  779.         {
  780.           warning (_("Unexpected number of hardware watchpoint registers"
  781.                      " reported by ptrace, got %d, expected %d."),
  782.                    aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
  783.           aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
  784.         }
  785.     }
  786.   else
  787.     {
  788.       warning (_("Unable to determine the number of hardware watchpoints"
  789.                  " available."));
  790.       aarch64_num_wp_regs = 0;
  791.     }

  793.   /* Get hardware breakpoint register info.  */
  794.   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
  795.       && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
  796.     {
  797.       aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
  798.       if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
  799.         {
  800.           warning (_("Unexpected number of hardware breakpoint registers"
  801.                      " reported by ptrace, got %d, expected %d."),
  802.                    aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
  803.           aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
  804.         }
  805.     }
  806.   else
  807.     {
  808.       warning (_("Unable to determine the number of hardware breakpoints"
  809.                  " available."));
  810.       aarch64_num_bp_regs = 0;
  811.     }
  812. }

  814. ‌static void (*super_post_startup_inferior) (struct target_ops *self,
  815.                                             ptid_t ptid);

  817. /* Implement the "to_post_startup_inferior" target_ops method.  */

  819. static void
  820. ‌aarch64_linux_child_post_startup_inferior (struct target_ops *self,
  821.                                            ptid_t ptid)
  822. {
  823.   aarch64_forget_process (ptid_get_pid (ptid));
  824.   aarch64_linux_get_debug_reg_capacity ();
  825.   super_post_startup_inferior (self, ptid);
  826. }

  828. /* Implement the "to_read_description" target_ops method.  */

  830. static const struct target_desc *
  831. ‌aarch64_linux_read_description (struct target_ops *ops)
  832. {
  833.   initialize_tdesc_aarch64 ();
  834.   return tdesc_aarch64;
  835. }

  837. /* Given the (potentially unaligned) watchpoint address in ADDR and
  838.    length in LEN, return the aligned address and aligned length in
  839.    *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively.  The returned
  840.    aligned address and length will be valid values to write to the
  841.    hardware watchpoint value and control registers.

  843.    The given watchpoint may get truncated if more than one hardware
  844.    register is needed to cover the watched region.  *NEXT_ADDR_P
  845.    and *NEXT_LEN_P, if non-NULL, will return the address and length
  846.    of the remaining part of the watchpoint (which can be processed
  847.    by calling this routine again to generate another aligned address
  848.    and length pair.

  850.    See the comment above the function of the same name in
  851.    gdbserver/linux-aarch64-low.c for more information.  */

  853. static void
  854. ‌aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
  855.                           int *aligned_len_p, CORE_ADDR *next_addr_p,
  856.                           int *next_len_p)
  857. {
  858.   int aligned_len;
  859.   unsigned int offset;
  860.   CORE_ADDR aligned_addr;
  861.   const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
  862.   const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;

  864.   /* As assumed by the algorithm.  */
  865.   gdb_assert (alignment == max_wp_len);

  867.   if (len <= 0)
  868.     return;

  870.   /* Address to be put into the hardware watchpoint value register
  871.      must be aligned.  */
  872.   offset = addr & (alignment - 1);
  873.   aligned_addr = addr - offset;

  875.   gdb_assert (offset >= 0 && offset < alignment);
  876.   gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
  877.   gdb_assert (offset + len > 0);

  879.   if (offset + len >= max_wp_len)
  880.     {
  881.       /* Need more than one watchpoint registers; truncate it at the
  882.          alignment boundary.  */
  883.       aligned_len = max_wp_len;
  884.       len -= (max_wp_len - offset);
  885.       addr += (max_wp_len - offset);
  886.       gdb_assert ((addr & (alignment - 1)) == 0);
  887.     }
  888.   else
  889.     {
  890.       /* Find the smallest valid length that is large enough to
  891.          accommodate this watchpoint.  */
  892.       static const unsigned char
  893.         aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
  894.         { 1, 2, 4, 4, 8, 8, 8, 8 };

  896.       aligned_len = aligned_len_array[offset + len - 1];
  897.       addr += len;
  898.       len = 0;
  899.     }

  901.   if (aligned_addr_p)
  902.     *aligned_addr_p = aligned_addr;
  903.   if (aligned_len_p)
  904.     *aligned_len_p = aligned_len;
  905.   if (next_addr_p)
  906.     *next_addr_p = addr;
  907.   if (next_len_p)
  908.     *next_len_p = len;
  909. }

  911. /* Returns the number of hardware watchpoints of type TYPE that we can
  912.    set.  Value is positive if we can set CNT watchpoints, zero if
  913.    setting watchpoints of type TYPE is not supported, and negative if
  914.    CNT is more than the maximum number of watchpoints of type TYPE
  915.    that we can support.  TYPE is one of bp_hardware_watchpoint,
  916.    bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
  917.    CNT is the number of such watchpoints used so far (including this
  918.    one).  OTHERTYPE is non-zero if other types of watchpoints are
  919.    currently enabled.

  921.    We always return 1 here because we don't have enough information
  922.    about possible overlap of addresses that they want to watch.  As an
  923.    extreme example, consider the case where all the watchpoints watch
  924.    the same address and the same region length: then we can handle a
  925.    virtually unlimited number of watchpoints, due to debug register
  926.    sharing implemented via reference counts.  */

  928. static int
  929. ‌aarch64_linux_can_use_hw_breakpoint (struct target_ops *self,
  930.                                      int type, int cnt, int othertype)
  931. {
  932.   return 1;
  933. }

  935. /* ptrace expects control registers to be formatted as follows:

  937.    31                             13          5      3      1     0
  938.    +--------------------------------+----------+------+------+----+
  939.    |         RESERVED (SBZ)         |  LENGTH  | TYPE | PRIV | EN |
  940.    +--------------------------------+----------+------+------+----+

  942.    The TYPE field is ignored for breakpoints.  */

  944. ‌#define DR_CONTROL_ENABLED(ctrl)        (((ctrl) & 0x1) == 1)
  945. ‌#define DR_CONTROL_LENGTH(ctrl)                (((ctrl) >> 5) & 0xff)

  947. /* Utility function that returns the length in bytes of a watchpoint
  948.    according to the content of a hardware debug control register CTRL.
  949.    Note that the kernel currently only supports the following Byte
  950.    Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
  951.    that for a hardware watchpoint, its valid length can only be 1
  952.    byte, 2 bytes, 4 bytes or 8 bytes.  */

  954. static inline unsigned int
  955. ‌aarch64_watchpoint_length (unsigned int ctrl)
  956. {
  957.   switch (DR_CONTROL_LENGTH (ctrl))
  958.     {
  959.     case 0x01:
  960.       return 1;
  961.     case 0x03:
  962.       return 2;
  963.     case 0x0f:
  964.       return 4;
  965.     case 0xff:
  966.       return 8;
  967.     default:
  968.       return 0;
  969.     }
  970. }

  972. /* Given the hardware breakpoint or watchpoint type TYPE and its
  973.    length LEN, return the expected encoding for a hardware
  974.    breakpoint/watchpoint control register.  */

  976. static unsigned int
  977. ‌aarch64_point_encode_ctrl_reg (int type, int len)
  978. {
  979.   unsigned int ctrl, ttype;

  981.   /* type */
  982.   switch (type)
  983.     {
  984.     case hw_write:
  985.       ttype = 2;
  986.       break;
  987.     case hw_read:
  988.       ttype = 1;
  989.       break;
  990.     case hw_access:
  991.       ttype = 3;
  992.       break;
  993.     case hw_execute:
  994.       ttype = 0;
  995.       break;
  996.     default:
  997.       perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
  998.     }
  999.   ctrl = ttype << 3;

  1001.   /* length bitmask */
  1002.   ctrl |= ((1 << len) - 1) << 5;
  1003.   /* enabled at el0 */
  1004.   ctrl |= (2 << 1) | 1;

  1006.   return ctrl;
  1007. }

  1009. /* Addresses to be written to the hardware breakpoint and watchpoint
  1010.    value registers need to be aligned; the alignment is 4-byte and
  1011.    8-type respectively.  Linux kernel rejects any non-aligned address
  1012.    it receives from the related ptrace call.  Furthermore, the kernel
  1013.    currently only supports the following Byte Address Select (BAS)
  1014.    values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
  1015.    watchpoint to be accepted by the kernel (via ptrace call), its
  1016.    valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
  1017.    Despite these limitations, the unaligned watchpoint is supported in
  1018.    this port.

  1020.    Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise.  */

  1022. static int
  1023. ‌aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
  1024. {
  1025.   unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
  1026.     : AARCH64_HBP_ALIGNMENT;

  1028.   if (addr & (alignment - 1))
  1029.     return 0;

  1031.   if (len != 8 && len != 4 && len != 2 && len != 1)
  1032.     return 0;

  1034.   return 1;
  1035. }

  1037. /* Record the insertion of one breakpoint/watchpoint, as represented
  1038.    by ADDR and CTRL, in the cached debug register state area *STATE.  */

  1040. static int
  1041. ‌aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
  1042.                                    int type, CORE_ADDR addr, int len)
  1043. {
  1044.   int i, idx, num_regs, is_watchpoint;
  1045.   unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
  1046.   CORE_ADDR *dr_addr_p;

  1048.   /* Set up state pointers.  */
  1049.   is_watchpoint = (type != hw_execute);
  1050.   gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
  1051.   if (is_watchpoint)
  1052.     {
  1053.       num_regs = aarch64_num_wp_regs;
  1054.       dr_addr_p = state->dr_addr_wp;
  1055.       dr_ctrl_p = state->dr_ctrl_wp;
  1056.       dr_ref_count = state->dr_ref_count_wp;
  1057.     }
  1058.   else
  1059.     {
  1060.       num_regs = aarch64_num_bp_regs;
  1061.       dr_addr_p = state->dr_addr_bp;
  1062.       dr_ctrl_p = state->dr_ctrl_bp;
  1063.       dr_ref_count = state->dr_ref_count_bp;
  1064.     }

  1066.   ctrl = aarch64_point_encode_ctrl_reg (type, len);

  1068.   /* Find an existing or free register in our cache.  */
  1069.   idx = -1;
  1070.   for (i = 0; i < num_regs; ++i)
  1071.     {
  1072.       if ((dr_ctrl_p[i] & 1) == 0)
  1073.         {
  1074.           gdb_assert (dr_ref_count[i] == 0);
  1075.           idx = i;
  1076.           /* no break; continue hunting for an existing one.  */
  1077.         }
  1078.       else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
  1079.         {
  1080.           gdb_assert (dr_ref_count[i] != 0);
  1081.           idx = i;
  1082.           break;
  1083.         }
  1084.     }

  1086.   /* No space.  */
  1087.   if (idx == -1)
  1088.     return -1;

  1090.   /* Update our cache.  */
  1091.   if ((dr_ctrl_p[idx] & 1) == 0)
  1092.     {
  1093.       /* new entry */
  1094.       dr_addr_p[idx] = addr;
  1095.       dr_ctrl_p[idx] = ctrl;
  1096.       dr_ref_count[idx] = 1;
  1097.       /* Notify the change.  */
  1098.       aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
  1099.     }
  1100.   else
  1101.     {
  1102.       /* existing entry */
  1103.       dr_ref_count[idx]++;
  1104.     }

  1106.   return 0;
  1107. }

  1109. /* Record the removal of one breakpoint/watchpoint, as represented by
  1110.    ADDR and CTRL, in the cached debug register state area *STATE.  */

  1112. static int
  1113. ‌aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
  1114.                                    int type, CORE_ADDR addr, int len)
  1115. {
  1116.   int i, num_regs, is_watchpoint;
  1117.   unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
  1118.   CORE_ADDR *dr_addr_p;

  1120.   /* Set up state pointers.  */
  1121.   is_watchpoint = (type != hw_execute);
  1122.   gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
  1123.   if (is_watchpoint)
  1124.     {
  1125.       num_regs = aarch64_num_wp_regs;
  1126.       dr_addr_p = state->dr_addr_wp;
  1127.       dr_ctrl_p = state->dr_ctrl_wp;
  1128.       dr_ref_count = state->dr_ref_count_wp;
  1129.     }
  1130.   else
  1131.     {
  1132.       num_regs = aarch64_num_bp_regs;
  1133.       dr_addr_p = state->dr_addr_bp;
  1134.       dr_ctrl_p = state->dr_ctrl_bp;
  1135.       dr_ref_count = state->dr_ref_count_bp;
  1136.     }

  1138.   ctrl = aarch64_point_encode_ctrl_reg (type, len);

  1140.   /* Find the entry that matches the ADDR and CTRL.  */
  1141.   for (i = 0; i < num_regs; ++i)
  1142.     if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
  1143.       {
  1144.         gdb_assert (dr_ref_count[i] != 0);
  1145.         break;
  1146.       }

  1148.   /* Not found.  */
  1149.   if (i == num_regs)
  1150.     return -1;

  1152.   /* Clear our cache.  */
  1153.   if (--dr_ref_count[i] == 0)
  1154.     {
  1155.       /* Clear the enable bit.  */
  1156.       ctrl &= ~1;
  1157.       dr_addr_p[i] = 0;
  1158.       dr_ctrl_p[i] = ctrl;
  1159.       /* Notify the change.  */
  1160.       aarch64_notify_debug_reg_change (state, is_watchpoint, i);
  1161.     }

  1163.   return 0;
  1164. }

  1166. /* Implement insertion and removal of a single breakpoint.  */

  1168. static int
  1169. ‌aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert)
  1170. {
  1171.   struct aarch64_debug_reg_state *state;

  1173.   /* The hardware breakpoint on AArch64 should always be 4-byte
  1174.      aligned.  */
  1175.   if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
  1176.     return -1;

  1178.   state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1180.   if (is_insert)
  1181.     return aarch64_dr_state_insert_one_point (state, type, addr, len);
  1182.   else
  1183.     return aarch64_dr_state_remove_one_point (state, type, addr, len);
  1184. }

  1186. /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address.
  1187.    Return 0 on success, -1 on failure.  */

  1189. static int
  1190. ‌aarch64_linux_insert_hw_breakpoint (struct target_ops *self,
  1191.                                     struct gdbarch *gdbarch,
  1192.                                     struct bp_target_info *bp_tgt)
  1193. {
  1194.   int ret;
  1195.   CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address;
  1196.   const int len = 4;
  1197.   const int type = hw_execute;

  1199.   if (show_debug_regs)
  1200.     fprintf_unfiltered
  1201.       (gdb_stdlog,
  1202.        "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
  1203.        (unsigned long) addr, len);

  1205.   ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */);

  1207.   if (show_debug_regs)
  1208.     {
  1209.       struct aarch64_debug_reg_state *state
  1210.         = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1212.       aarch64_show_debug_reg_state (state,
  1213.                                     "insert_hw_watchpoint", addr, len, type);
  1214.     }

  1216.   return ret;
  1217. }

  1219. /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
  1220.    Return 0 on success, -1 on failure.  */

  1222. static int
  1223. ‌aarch64_linux_remove_hw_breakpoint (struct target_ops *self,
  1224.                                     struct gdbarch *gdbarch,
  1225.                                     struct bp_target_info *bp_tgt)
  1226. {
  1227.   int ret;
  1228.   CORE_ADDR addr = bp_tgt->placed_address;
  1229.   const int len = 4;
  1230.   const int type = hw_execute;

  1232.   if (show_debug_regs)
  1233.     fprintf_unfiltered
  1234.       (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
  1235.        (unsigned long) addr, len);

  1237.   ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */);

  1239.   if (show_debug_regs)
  1240.     {
  1241.       struct aarch64_debug_reg_state *state
  1242.         = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1244.       aarch64_show_debug_reg_state (state,
  1245.                                     "remove_hw_watchpoint", addr, len, type);
  1246.     }

  1248.   return ret;
  1249. }

  1251. /* This is essentially the same as aarch64_handle_breakpoint, apart
  1252.    from that it is an aligned watchpoint to be handled.  */

  1254. static int
  1255. ‌aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len,
  1256.                                    int is_insert)
  1257. {
  1258.   struct aarch64_debug_reg_state *state
  1259.     = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1261.   if (is_insert)
  1262.     return aarch64_dr_state_insert_one_point (state, type, addr, len);
  1263.   else
  1264.     return aarch64_dr_state_remove_one_point (state, type, addr, len);
  1265. }

  1267. /* Insert/remove unaligned watchpoint by calling
  1268.    aarch64_align_watchpoint repeatedly until the whole watched region,
  1269.    as represented by ADDR and LEN, has been properly aligned and ready
  1270.    to be written to one or more hardware watchpoint registers.
  1271.    IS_INSERT indicates whether this is an insertion or a deletion.
  1272.    Return 0 if succeed.  */

  1274. static int
  1275. ‌aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len,
  1276.                                      int is_insert)
  1277. {
  1278.   struct aarch64_debug_reg_state *state
  1279.     = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1281.   while (len > 0)
  1282.     {
  1283.       CORE_ADDR aligned_addr;
  1284.       int aligned_len, ret;

  1286.       aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
  1287.                                 &addr, &len);

  1289.       if (is_insert)
  1290.         ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
  1291.                                                  aligned_len);
  1292.       else
  1293.         ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
  1294.                                                  aligned_len);

  1296.       if (show_debug_regs)
  1297.         fprintf_unfiltered (gdb_stdlog,
  1298. "handle_unaligned_watchpoint: is_insert: %d\n"
  1299. "                             aligned_addr: 0x%08lx, aligned_len: %d\n"
  1300. "                                next_addr: 0x%08lx,    next_len: %d\n",
  1301.                  is_insert, aligned_addr, aligned_len, addr, len);

  1303.       if (ret != 0)
  1304.         return ret;
  1305.     }

  1307.   return 0;
  1308. }

  1310. /* Implements insertion and removal of a single watchpoint.  */

  1312. static int
  1313. ‌aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert)
  1314. {
  1315.   if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
  1316.     return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert);
  1317.   else
  1318.     return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert);
  1319. }

  1321. /* Implement the "to_insert_watchpoint" target_ops method.

  1323.    Insert a watchpoint to watch a memory region which starts at
  1324.    address ADDR and whose length is LEN bytes.  Watch memory accesses
  1325.    of the type TYPE.  Return 0 on success, -1 on failure.  */

  1327. static int
  1328. ‌aarch64_linux_insert_watchpoint (struct target_ops *self,
  1329.                                  CORE_ADDR addr, int len, int type,
  1330.                                  struct expression *cond)
  1331. {
  1332.   int ret;

  1334.   if (show_debug_regs)
  1335.     fprintf_unfiltered (gdb_stdlog,
  1336.                         "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
  1337.                         (unsigned long) addr, len);

  1339.   gdb_assert (type != hw_execute);

  1341.   ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */);

  1343.   if (show_debug_regs)
  1344.     {
  1345.       struct aarch64_debug_reg_state *state
  1346.         = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1348.       aarch64_show_debug_reg_state (state,
  1349.                                     "insert_watchpoint", addr, len, type);
  1350.     }

  1352.   return ret;
  1353. }

  1355. /* Implement the "to_remove_watchpoint" target_ops method.
  1356.    Remove a watchpoint that watched the memory region which starts at
  1357.    address ADDR, whose length is LEN bytes, and for accesses of the
  1358.    type TYPE.  Return 0 on success, -1 on failure.  */

  1360. static int
  1361. ‌aarch64_linux_remove_watchpoint (struct target_ops *self,
  1362.                                  CORE_ADDR addr, int len, int type,
  1363.                                  struct expression *cond)
  1364. {
  1365.   int ret;

  1367.   if (show_debug_regs)
  1368.     fprintf_unfiltered (gdb_stdlog,
  1369.                         "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
  1370.                         (unsigned long) addr, len);

  1372.   gdb_assert (type != hw_execute);

  1374.   ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */);

  1376.   if (show_debug_regs)
  1377.     {
  1378.       struct aarch64_debug_reg_state *state
  1379.         = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));

  1381.       aarch64_show_debug_reg_state (state,
  1382.                                     "remove_watchpoint", addr, len, type);
  1383.     }

  1385.   return ret;
  1386. }

  1388. /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method.  */

  1390. static int
  1391. ‌aarch64_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
  1392.                                            CORE_ADDR addr, int len)
  1393. {
  1394.   CORE_ADDR aligned_addr;

  1396.   /* Can not set watchpoints for zero or negative lengths.  */
  1397.   if (len <= 0)
  1398.     return 0;

  1400.   /* Must have hardware watchpoint debug register(s).  */
  1401.   if (aarch64_num_wp_regs == 0)
  1402.     return 0;

  1404.   /* We support unaligned watchpoint address and arbitrary length,
  1405.      as long as the size of the whole watched area after alignment
  1406.      doesn't exceed size of the total area that all watchpoint debug
  1407.      registers can watch cooperatively.

  1409.      This is a very relaxed rule, but unfortunately there are
  1410.      limitations, e.g. false-positive hits, due to limited support of
  1411.      hardware debug registers in the kernel.  See comment above
  1412.      aarch64_align_watchpoint for more information.  */

  1414.   aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1);
  1415.   if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG
  1416.       < addr + len)
  1417.     return 0;

  1419.   /* All tests passed so we are likely to be able to set the watchpoint.
  1420.      The reason that it is 'likely' rather than 'must' is because
  1421.      we don't check the current usage of the watchpoint registers, and
  1422.      there may not be enough registers available for this watchpoint.
  1423.      Ideally we should check the cached debug register state, however
  1424.      the checking is costly.  */
  1425.   return 1;
  1426. }

  1428. /* Implement the "to_stopped_data_address" target_ops method.  */

  1430. static int
  1431. ‌aarch64_linux_stopped_data_address (struct target_ops *target,
  1432.                                     CORE_ADDR *addr_p)
  1433. {
  1434.   siginfo_t siginfo;
  1435.   int i, tid;
  1436.   struct aarch64_debug_reg_state *state;

  1438.   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
  1439.     return 0;

  1441.   /* This must be a hardware breakpoint.  */
  1442.   if (siginfo.si_signo != SIGTRAP
  1443.       || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
  1444.     return 0;

  1446.   /* Check if the address matches any watched address.  */
  1447.   state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
  1448.   for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
  1449.     {
  1450.       const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
  1451.       const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
  1452.       const CORE_ADDR addr_watch = state->dr_addr_wp[i];

  1454.       if (state->dr_ref_count_wp[i]
  1455.           && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
  1456.           && addr_trap >= addr_watch
  1457.           && addr_trap < addr_watch + len)
  1458.         {
  1459.           *addr_p = addr_trap;
  1460.           return 1;
  1461.         }
  1462.     }

  1464.   return 0;
  1465. }

  1467. /* Implement the "to_stopped_by_watchpoint" target_ops method.  */

  1469. static int
  1470. ‌aarch64_linux_stopped_by_watchpoint (struct target_ops *ops)
  1471. {
  1472.   CORE_ADDR addr;

  1474.   return aarch64_linux_stopped_data_address (ops, &addr);
  1475. }

  1477. /* Implement the "to_watchpoint_addr_within_range" target_ops method.  */

  1479. static int
  1480. ‌aarch64_linux_watchpoint_addr_within_range (struct target_ops *target,
  1481.                                             CORE_ADDR addr,
  1482.                                             CORE_ADDR start, int length)
  1483. {
  1484.   return start <= addr && start + length - 1 >= addr;
  1485. }

  1487. /* Define AArch64 maintenance commands.  */

  1489. static void
  1490. ‌add_show_debug_regs_command (void)
  1491. {
  1492.   /* A maintenance command to enable printing the internal DRi mirror
  1493.      variables.  */
  1494.   add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
  1495.                            &show_debug_regs, _("\
  1496. Set whether to show variables that mirror the AArch64 debug registers."), _("\
  1497. Show whether to show variables that mirror the AArch64 debug registers."), _("\
  1498. Use \"on\" to enable, \"off\" to disable.\n\
  1499. If enabled, the debug registers values are shown when GDB inserts\n\
  1500. or removes a hardware breakpoint or watchpoint, and when the inferior\n\
  1501. triggers a breakpoint or watchpoint."),
  1502.                            NULL,
  1503.                            NULL,
  1504.                            &maintenance_set_cmdlist,
  1505.                            &maintenance_show_cmdlist);
  1506. }

  1508. /* -Wmissing-prototypes.  */
  1509. void _initialize_aarch64_linux_nat (void);

  1511. void
  1512. ‌_initialize_aarch64_linux_nat (void)
  1513. {
  1514.   struct target_ops *t;

  1516.   /* Fill in the generic GNU/Linux methods.  */
  1517.   t = linux_target ();

  1519.   add_show_debug_regs_command ();

  1521.   /* Add our register access methods.  */
  1522.   t->to_fetch_registers = aarch64_linux_fetch_inferior_registers;
  1523.   t->to_store_registers = aarch64_linux_store_inferior_registers;

  1525.   t->to_read_description = aarch64_linux_read_description;

  1527.   t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint;
  1528.   t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint;
  1529.   t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint;
  1530.   t->to_region_ok_for_hw_watchpoint =
  1531.     aarch64_linux_region_ok_for_hw_watchpoint;
  1532.   t->to_insert_watchpoint = aarch64_linux_insert_watchpoint;
  1533.   t->to_remove_watchpoint = aarch64_linux_remove_watchpoint;
  1534.   t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint;
  1535.   t->to_stopped_data_address = aarch64_linux_stopped_data_address;
  1536.   t->to_watchpoint_addr_within_range =
  1537.     aarch64_linux_watchpoint_addr_within_range;

  1539.   /* Override the GNU/Linux inferior startup hook.  */
  1540.   super_post_startup_inferior = t->to_post_startup_inferior;
  1541.   t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior;

  1543.   /* Register the target.  */
  1544.   linux_nat_add_target (t);
  1545.   linux_nat_set_new_thread (t, aarch64_linux_new_thread);
  1546.   linux_nat_set_new_fork (t, aarch64_linux_new_fork);
  1547.   linux_nat_set_forget_process (t, aarch64_forget_process);
  1548.   linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume);
  1549. }