src/longlong.h - coreutils-8.23
Macros defined
Source code
#define __BITS4 (W_TYPE_SIZE / 4)
#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
#ifndef __MPN
#define __MPN(x) __##x
#endif
#ifdef _LONG_LONG_LIMB
#define count_leading_zeros_gcc_clz(count,x) \
do { \
ASSERT ((x) != 0); \
(count) = __builtin_clzll (x); \
} while (0)
#else
#define count_leading_zeros_gcc_clz(count,x) \
do { \
ASSERT ((x) != 0); \
(count) = __builtin_clzl (x); \
} while (0)
#endif
#ifdef _LONG_LONG_LIMB
#define count_trailing_zeros_gcc_ctz(count,x) \
do { \
ASSERT ((x) != 0); \
(count) = __builtin_ctzll (x); \
} while (0)
#else
#define count_trailing_zeros_gcc_ctz(count,x) \
do { \
ASSERT ((x) != 0); \
(count) = __builtin_ctzl (x); \
} while (0)
#endif
FIXME#if ! defined (NO_ASM)
#if defined (__alpha) && W_TYPE_SIZE == 64
#if defined (__GNUC__)
#if __GMP_GNUC_PREREQ (3,3)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
(ph) = __builtin_alpha_umulh (__m0, __m1); \
(pl) = __m0 * __m1; \
} while (0)
#else
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
__asm__ ("umulh %r1,%2,%0" \
: "=r" (ph) \
: "%rJ" (m0), "rI" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#endif
#define UMUL_TIME 18
#else #include <machine/builtins.h>
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
(ph) = __UMULH (m0, m1); \
(pl) = __m0 * __m1; \
} while (0)
#endif
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UWtype __di; \
__di = __MPN(invert_limb) (d); \
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
} while (0)
#define UDIV_PREINV_ALWAYS 1
#define UDIV_NEEDS_NORMALIZATION 1
#define UDIV_TIME 220
#endif
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
#if defined (__GNUC__) && HAVE_HOST_CPU_alpha_CIX
#define count_leading_zeros(COUNT,X) \
__asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
#define count_trailing_zeros(COUNT,X) \
__asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
#endif
#if ! defined (count_leading_zeros) \
&& defined (__GNUC__) && ! defined (LONGLONG_STANDALONE)
#define ALPHA_CMPBGE_0(dst, src) \
do { asm ("cmpbge $31, %1, %0" : "=r" (dst) : "r" (src)); } while (0)
#define count_leading_zeros(count, x) \
do { \
UWtype __clz__b, __clz__c, __clz__x = (x); \
ALPHA_CMPBGE_0 (__clz__b, __clz__x); \
__clz__b = __clz_tab [(__clz__b >> 1) ^ 0x7F]; \
__clz__b = __clz__b * 8 - 7; \
__clz__x >>= __clz__b; \
__clz__c = __clz_tab [__clz__x]; \
__clz__b = 65 - __clz__b; \
(count) = __clz__b - __clz__c; \
} while (0)
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
#endif
#if ! defined (count_leading_zeros) && ! defined (LONGLONG_STANDALONE)
#if HAVE_ATTRIBUTE_CONST
long __MPN(count_leading_zeros) (UDItype) __attribute__ ((const));
#else
long __MPN(count_leading_zeros) (UDItype);
#endif
#define count_leading_zeros(count, x) \
((count) = __MPN(count_leading_zeros) (x))
#endif #endif
#if defined (__AVR) && W_TYPE_SIZE == 8
#define umul_ppmm(ph, pl, m0, m1) \
do { \
unsigned short __p = (unsigned short) (m0) * (m1); \
(ph) = __p >> 8; \
(pl) = __p; \
} while (0)
#endif
#if defined (_CRAY) && W_TYPE_SIZE == 64
#include <intrinsics.h>
#define UDIV_PREINV_ALWAYS 1
#define UDIV_NEEDS_NORMALIZATION 1
#define UDIV_TIME 220
long __MPN(count_leading_zeros) (UDItype);
#define count_leading_zeros(count, x) \
((count) = _leadz ((UWtype) (x)))
#if defined (_CRAYIEEE) #define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
(ph) = _int_mult_upper (m0, m1); \
(pl) = __m0 * __m1; \
} while (0)
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UWtype __di; \
__di = __MPN(invert_limb) (d); \
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
} while (0)
#endif #endif #endif
#if defined (__ia64) && W_TYPE_SIZE == 64
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
UWtype __x; \
__x = (al) - (bl); \
if ((al) < (bl)) \
(sh) = (ah) - (bh) - 1; \
else \
(sh) = (ah) - (bh); \
(sl) = __x; \
} while (0)
#if defined (__GNUC__) && ! defined (__INTEL_COMPILER)
#define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
: "=&f" (ph), "=f" (pl) \
: "f" (m0), "f" (m1))
#define UMUL_TIME 14
#define count_leading_zeros(count, x) \
do { \
UWtype _x = (x), _y, _a, _c; \
__asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
__asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
_c = (_a - 1) << 3; \
_x >>= _c; \
if (_x >= 1 << 4) \
_x >>= 4, _c += 4; \
if (_x >= 1 << 2) \
_x >>= 2, _c += 2; \
_c += _x >> 1; \
(count) = W_TYPE_SIZE - 1 - _c; \
} while (0)
#define count_trailing_zeros(count, x) \
do { \
UWtype __ctz_x = (x); \
__asm__ ("popcnt %0 = %1" \
: "=r" (count) \
: "r" ((__ctz_x-1) & ~__ctz_x)); \
} while (0)
#endif
#if defined (__INTEL_COMPILER)
#include <ia64intrin.h>
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UWtype _m0 = (m0), _m1 = (m1); \
ph = _m64_xmahu (_m0, _m1, 0); \
pl = _m0 * _m1; \
} while (0)
#endif
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UWtype __di; \
__di = __MPN(invert_limb) (d); \
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
} while (0)
#define UDIV_PREINV_ALWAYS 1
#define UDIV_NEEDS_NORMALIZATION 1
#endif
#define UDIV_TIME 220
#endif
#if defined (__GNUC__)
#if __GNUC__ < 2
#define __CLOBBER_CC
#define __AND_CLOBBER_CC
#else #define __CLOBBER_CC : "cc"
#define __AND_CLOBBER_CC , "cc"
#endif
#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %1,%4,%5\n\taddc %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "rI" (bh), "%r" (al), "rI" (bl))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %1,%4,%5\n\tsubc %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "rI" (bh), "r" (al), "rI" (bl))
#define umul_ppmm(xh, xl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("multiplu %0,%1,%2" \
: "=r" (xl) \
: "r" (__m0), "r" (__m1)); \
__asm__ ("multmu %0,%1,%2" \
: "=r" (xh) \
: "r" (__m0), "r" (__m1)); \
} while (0)
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("dividu %0,%3,%4" \
: "=r" (q), "=q" (r) \
: "1" (n1), "r" (n0), "r" (d))
#define count_leading_zeros(count, x) \
__asm__ ("clz %0,%1" \
: "=r" (count) \
: "r" (x))
#define COUNT_LEADING_ZEROS_0 32
#endif
#if defined (__arc__)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.f\t%1, %4, %5\n\tadc\t%0, %2, %3" \
: "=r" (sh), \
"=&r" (sl) \
: "r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.f\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
: "=r" (sh), \
"=&r" (sl) \
: "r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
#endif
#if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("adds\t%1, %4, %5\n\tadc\t%0, %2, %3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "rI" (bh), "%r" (al), "rI" (bl) __CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (al)) \
{ \
if (__builtin_constant_p (ah)) \
__asm__ ("rsbs\t%1, %5, %4\n\trsc\t%0, %3, %2" \
: "=r" (sh), "=&r" (sl) \
: "rI" (ah), "r" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \
else \
__asm__ ("rsbs\t%1, %5, %4\n\tsbc\t%0, %2, %3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "rI" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \
} \
else if (__builtin_constant_p (ah)) \
{ \
if (__builtin_constant_p (bl)) \
__asm__ ("subs\t%1, %4, %5\n\trsc\t%0, %3, %2" \
: "=r" (sh), "=&r" (sl) \
: "rI" (ah), "r" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \
else \
__asm__ ("rsbs\t%1, %5, %4\n\trsc\t%0, %3, %2" \
: "=r" (sh), "=&r" (sl) \
: "rI" (ah), "r" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \
} \
else if (__builtin_constant_p (bl)) \
{ \
if (__builtin_constant_p (bh)) \
__asm__ ("subs\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "rI" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \
else \
__asm__ ("subs\t%1, %4, %5\n\trsc\t%0, %3, %2" \
: "=r" (sh), "=&r" (sl) \
: "rI" (ah), "r" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \
} \
else \
__asm__ ("subs\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "rI" (bh), "r" (al), "rI" (bl) __CLOBBER_CC);\
} while (0)
#if 1 || defined (__arm_m__) #define umul_ppmm(xh, xl, a, b) \
__asm__ ("umull %0,%1,%2,%3" : "=&r" (xl), "=&r" (xh) : "r" (a), "r" (b))
#define UMUL_TIME 5
#define smul_ppmm(xh, xl, a, b) \
__asm__ ("smull %0,%1,%2,%3" : "=&r" (xl), "=&r" (xh) : "r" (a), "r" (b))
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UWtype __di; \
__di = __MPN(invert_limb) (d); \
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
} while (0)
#define UDIV_PREINV_ALWAYS 1
#define UDIV_NEEDS_NORMALIZATION 1
#define UDIV_TIME 70
#endif #else
#endif
#if defined (__ARM_ARCH_5__) || defined (__ARM_ARCH_5T__) || \
defined (__ARM_ARCH_5E__) || defined (__ARM_ARCH_5TE__)|| \
defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) || \
defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) || \
defined (__ARM_ARCH_6ZK__)|| defined (__ARM_ARCH_6T2__)|| \
defined (__ARM_ARCH_6M__) || defined (__ARM_ARCH_7__) || \
defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) || \
defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#define count_leading_zeros(count, x) \
__asm__ ("clz\t%0, %1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 32
#endif
#endif
#if defined (__aarch64__) && W_TYPE_SIZE == 64
FIXME#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("adds\t%1, %x4, %5\n\tadc\t%0, %x2, %x3" \
: "=r" (sh), "=&r" (sl) \
: "rZ" (ah), "rZ" (bh), "%r" (al), "rI" (bl) __CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subs\t%1, %x4, %5\n\tsbc\t%0, %x2, %x3" \
: "=r,r" (sh), "=&r,&r" (sl) \
: "rZ,rZ" (ah), "rZ,rZ" (bh), "r,Z" (al), "rI,r" (bl) __CLOBBER_CC)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
__asm__ ("umulh\t%0, %1, %2" : "=r" (ph) : "r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define count_leading_zeros(count, x) \
__asm__ ("clz\t%0, %1" : "=r" (count) : "r" (x))
#define count_trailing_zeros(count, x) \
__asm__ ("rbit\t%0, %1\n\tclz\t%0, %0" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 64
#endif
#if defined (__clipper__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __x; \
__asm__ ("mulwux %2,%0" \
: "=r" (__x.__ll) \
: "%0" ((USItype)(u)), "r" ((USItype)(v))); \
(w1) = __x.__i.__h; (w0) = __x.__i.__l;})
#define smul_ppmm(w1, w0, u, v) \
({union {DItype __ll; \
struct {SItype __l, __h;} __i; \
} __x; \
__asm__ ("mulwx %2,%0" \
: "=r" (__x.__ll) \
: "%0" ((SItype)(u)), "r" ((SItype)(v))); \
(w1) = __x.__i.__h; (w0) = __x.__i.__l;})
#define __umulsidi3(u, v) \
({UDItype __w; \
__asm__ ("mulwux %2,%0" \
: "=r" (__w) : "%0" ((USItype)(u)), "r" ((USItype)(v))); \
__w; })
#endif
#if defined (__uxp__) && W_TYPE_SIZE == 32
#define umul_ppmm(ph, pl, u, v) \
do { \
union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("mult.lu %1,%2,%0" : "=r" (__x.__ll) : "%r" (u), "rK" (v));\
(ph) = __x.__i.__h; \
(pl) = __x.__i.__l; \
} while (0)
#define smul_ppmm(ph, pl, u, v) \
do { \
union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("mult.l %1,%2,%0" : "=r" (__x.__ll) : "%r" (u), "rK" (v)); \
(ph) = __x.__i.__h; \
(pl) = __x.__i.__l; \
} while (0)
#endif
#if defined (__gmicro__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.w %5,%1\n\taddx %3,%0" \
: "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.w %5,%1\n\tsubx %3,%0" \
: "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("mulx %3,%0,%1" \
: "=g" (ph), "=r" (pl) \
: "%0" ((USItype)(m0)), "g" ((USItype)(m1)))
#define udiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("divx %4,%0,%1" \
: "=g" (q), "=r" (r) \
: "1" ((USItype)(nh)), "0" ((USItype)(nl)), "g" ((USItype)(d)))
#define count_leading_zeros(count, x) \
__asm__ ("bsch/1 %1,%0" \
: "=g" (count) : "g" ((USItype)(x)), "0" ((USItype)0))
#endif
#if defined (__hppa) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%I5 %5,%r4,%1\n\taddc %r2,%r3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rM" (ah), "rM" (bh), "%rM" (al), "rI" (bl))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%I4 %4,%r5,%1\n\tsubb %r2,%r3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rM" (ah), "rM" (bh), "rI" (al), "rM" (bl))
#if defined (_PA_RISC1_1)
#define umul_ppmm(wh, wl, u, v) \
do { \
union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("xmpyu %1,%2,%0" : "=*f" (__x.__ll) : "*f" (u), "*f" (v)); \
(wh) = __x.__i.__h; \
(wl) = __x.__i.__l; \
} while (0)
#define UMUL_TIME 8
#define UDIV_TIME 60
#else
#define UMUL_TIME 40
#define UDIV_TIME 80
#endif
#define count_leading_zeros(count, x) \
do { \
USItype __tmp; \
__asm__ ( \
"ldi 1,%0\n" \
" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
" ldo 16(%0),%0 ; Yes. Perform add.\n" \
" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
" ldo 8(%0),%0 ; Yes. Perform add.\n" \
" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
" ldo 4(%0),%0 ; Yes. Perform add.\n" \
" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
" ldo 2(%0),%0 ; Yes. Perform add.\n" \
" extru %1,30,1,%1 ; Extract bit 1.\n" \
" sub %0,%1,%0 ; Subtract it.\n" \
: "=r" (count), "=r" (__tmp) : "1" (x)); \
} while (0)
#endif
#if defined (__hppa) && W_TYPE_SIZE == 64 && ! defined (_LONG_LONG_LIMB)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%I5 %5,%r4,%1\n\tadd,dc %r2,%r3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rM" (ah), "rM" (bh), "%rM" (al), "rI" (bl))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%I4 %4,%r5,%1\n\tsub,db %r2,%r3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rM" (ah), "rM" (bh), "rI" (al), "rM" (bl))
#endif
#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
#if defined (__zarch__) || defined (HAVE_HOST_CPU_s390_zarch)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
__asm__ ("alr\t%1,%5\n\talcr\t%0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" (ah), "r" (bh), "%1" (al), "r" (bl)__CLOBBER_CC); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
__asm__ ("slr\t%1,%5\n\tslbr\t%0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" (ah), "r" (bh), "1" (al), "r" (bl) __CLOBBER_CC); \
} while (0)
#if __GMP_GNUC_PREREQ (4,5)
#define umul_ppmm(xh, xl, m0, m1) \
do { \
union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__x.__ll = (UDItype) (m0) * (UDItype) (m1); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0)
#else
#if 0
#else
#define umul_ppmm(xh, xl, m0, m1) \
do { \
\
register USItype __r0 __asm__ ("0"); \
register USItype __r1 __asm__ ("1") = (m0); \
__asm__ ("mlr\t%0,%3" \
: "=r" (__r0), "=r" (__r1) \
: "r" (__r1), "r" (m1)); \
(xh) = __r0; (xl) = __r1; \
} while (0)
#endif #endif
#if 0
#else
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
register USItype __r0 __asm__ ("0") = (n1); \
register USItype __r1 __asm__ ("1") = (n0); \
__asm__ ("dlr\t%0,%4" \
: "=r" (__r0), "=r" (__r1) \
: "r" (__r0), "r" (__r1), "r" (d)); \
(q) = __r1; (r) = __r0; \
} while (0)
#endif #else FIXME#define smul_ppmm(xh, xl, m0, m1) \
do { \
union {DItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("mr\t%0,%2" \
: "=r" (__x.__ll) \
: "%0" (m0), "r" (m1)); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0)
FIXME#define sdiv_qrnnd(q, r, n1, n0, d) \
do { \
union {DItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("dr\t%0,%2" \
: "=r" (__x.__ll) \
: "0" (__x.__ll), "r" (d)); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0)
#endif #endif
#if defined (__s390x__) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
__asm__ ("algr\t%1,%5\n\talcgr\t%0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "r" ((UDItype)(bh)), \
"%1" ((UDItype)(al)), "r" ((UDItype)(bl)) __CLOBBER_CC); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
__asm__ ("slgr\t%1,%5\n\tslbgr\t%0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "r" ((UDItype)(bh)), \
"1" ((UDItype)(al)), "r" ((UDItype)(bl)) __CLOBBER_CC); \
} while (0)
#define umul_ppmm(xh, xl, m0, m1) \
do { \
union {unsigned int __attribute__ ((mode(TI))) __ll; \
struct {UDItype __h, __l;} __i; \
} __x; \
__asm__ ("mlgr\t%0,%2" \
: "=r" (__x.__ll) \
: "%0" ((UDItype)(m0)), "r" ((UDItype)(m1))); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0)
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
union {unsigned int __attribute__ ((mode(TI))) __ll; \
struct {UDItype __h, __l;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("dlgr\t%0,%2" \
: "=r" (__x.__ll) \
: "0" (__x.__ll), "r" ((UDItype)(d))); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0)
#if 0#endif
#endif
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl %5,%k1\n\tadcl %3,%k0" \
: "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl %5,%k1\n\tsbbl %3,%k0" \
: "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mull %3" \
: "=a" (w0), "=d" (w1) \
: "%0" ((USItype)(u)), "rm" ((USItype)(v)))
#define udiv_qrnnd(q, r, n1, n0, dx) \
__asm__ ("divl %4" \
: "=a" (q), "=d" (r) \
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "rm" ((USItype)(dx)))
#if HAVE_HOST_CPU_i586 || HAVE_HOST_CPU_pentium || HAVE_HOST_CPU_pentiummmx
#if HAVE_HOST_CPU_pentiummmx && ! defined (LONGLONG_STANDALONE)
#define count_leading_zeros(c,n) \
do { \
USItype __n = (n); \
USItype __shift; \
__asm__ ("cmpl $0x1000000, %1\n" \
"sbbl %0, %0\n" \
"cmpl $0x10000, %1\n" \
"sbbl $0, %0\n" \
"cmpl $0x100, %1\n" \
"sbbl $0, %0\n" \
: "=&r" (__shift) : "r" (__n)); \
__shift = __shift*8 + 24 + 1; \
(c) = 32 + 1 - __shift - __clz_tab[__n >> __shift]; \
} while (0)
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
#define COUNT_LEADING_ZEROS_0 31
#else #define count_leading_zeros(c,n) \
do { \
union { \
double d; \
unsigned a[2]; \
} __u; \
ASSERT ((n) != 0); \
__u.d = (UWtype) (n); \
(c) = 0x3FF + 31 - (__u.a[1] >> 20); \
} while (0)
#define COUNT_LEADING_ZEROS_0 (0x3FF + 31)
#endif
#else
#if __GMP_GNUC_PREREQ (3,4) #define count_leading_zeros(count,x) count_leading_zeros_gcc_clz(count,x)
#endif
#if ! defined (count_leading_zeros) && __GNUC__ < 3 \
&& (HAVE_HOST_CPU_i386 \
|| HAVE_HOST_CPU_i686 \
|| HAVE_HOST_CPU_pentiumpro \
|| HAVE_HOST_CPU_pentium2 \
|| HAVE_HOST_CPU_pentium3)
#define count_leading_zeros(count, x) \
do { \
USItype __cbtmp; \
ASSERT ((x) != 0); \
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
(count) = 31 - __cbtmp; \
} while (0)
#endif
#ifndef count_leading_zeros
#define count_leading_zeros(count, x) \
do { \
USItype __cbtmp; \
ASSERT ((x) != 0); \
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
(count) = __cbtmp ^ 31; \
} while (0)
#endif
#if __GMP_GNUC_PREREQ (3,4) #define count_trailing_zeros(count,x) count_trailing_zeros_gcc_ctz(count,x)
#endif
#ifndef count_trailing_zeros
#define count_trailing_zeros(count, x) \
do { \
ASSERT ((x) != 0); \
__asm__ ("bsfl %1,%k0" : "=r" (count) : "rm" ((USItype)(x))); \
} while (0)
#endif
#endif
#ifndef UMUL_TIME
#define UMUL_TIME 10
#endif
#ifndef UDIV_TIME
#define UDIV_TIME 40
#endif
#endif
#if defined (__amd64__) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addq %5,%q1\n\tadcq %3,%q0" \
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "rme" ((UDItype)(bh)), \
"%1" ((UDItype)(al)), "rme" ((UDItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subq %5,%q1\n\tsbbq %3,%q0" \
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "rme" ((UDItype)(bh)), \
"1" ((UDItype)(al)), "rme" ((UDItype)(bl)))
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulq %3" \
: "=a" (w0), "=d" (w1) \
: "%0" ((UDItype)(u)), "rm" ((UDItype)(v)))
#define udiv_qrnnd(q, r, n1, n0, dx) \
__asm__ ("divq %4" \
: "=a" (q), "=d" (r) \
: "0" ((UDItype)(n0)), "1" ((UDItype)(n1)), "rm" ((UDItype)(dx)))
#define count_leading_zeros(count, x) \
do { \
UDItype __cbtmp; \
ASSERT ((x) != 0); \
__asm__ ("bsrq %1,%0" : "=r" (__cbtmp) : "rm" ((UDItype)(x))); \
(count) = __cbtmp ^ 63; \
} while (0)
#define count_trailing_zeros(count, x) \
do { \
ASSERT ((x) != 0); \
__asm__ ("bsfq %1,%q0" : "=r" (count) : "rm" ((UDItype)(x))); \
} while (0)
#endif
#if defined (__i860__) && W_TYPE_SIZE == 32
#define rshift_rhlc(r,h,l,c) \
__asm__ ("shr %3,r0,r0\;shrd %1,%2,%0" \
"=r" (r) : "r" (h), "r" (l), "rn" (c))
#endif
#if defined (__i960__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("cmpo 1,0\;addc %5,%4,%1\;addc %3,%2,%0" \
: "=r" (sh), "=&r" (sl) \
: "dI" (ah), "dI" (bh), "%dI" (al), "dI" (bl))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("cmpo 0,0\;subc %5,%4,%1\;subc %3,%2,%0" \
: "=r" (sh), "=&r" (sl) \
: "dI" (ah), "dI" (bh), "dI" (al), "dI" (bl))
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __x; \
__asm__ ("emul %2,%1,%0" \
: "=d" (__x.__ll) : "%dI" (u), "dI" (v)); \
(w1) = __x.__i.__h; (w0) = __x.__i.__l;})
#define __umulsidi3(u, v) \
({UDItype __w; \
__asm__ ("emul %2,%1,%0" : "=d" (__w) : "%dI" (u), "dI" (v)); \
__w; })
#define udiv_qrnnd(q, r, nh, nl, d) \
do { \
union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __nn; \
__nn.__i.__h = (nh); __nn.__i.__l = (nl); \
__asm__ ("ediv %d,%n,%0" \
: "=d" (__rq.__ll) : "dI" (__nn.__ll), "dI" (d)); \
(r) = __rq.__i.__l; (q) = __rq.__i.__h; \
} while (0)
#define count_leading_zeros(count, x) \
do { \
USItype __cbtmp; \
__asm__ ("scanbit %1,%0" : "=r" (__cbtmp) : "r" (x)); \
(count) = __cbtmp ^ 31; \
} while (0)
#define COUNT_LEADING_ZEROS_0 (-32) #if defined (__i960mx) #define rshift_rhlc(r,h,l,c) \
do { \
union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __nn; \
__nn.__i.__h = (h); __nn.__i.__l = (l); \
__asm__ ("shre %2,%1,%0" : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \
}
#endif #endif
#if (defined (__mc68000__) || defined (__mc68020__) || defined(mc68020) \
|| defined (__m68k__) || defined (__mc5200__) || defined (__mc5206e__) \
|| defined (__mc5307__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
: "=d" (sh), "=&d" (sl) \
: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
: "=d" (sh), "=&d" (sl) \
: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#if defined (__mc68020__) || defined(mc68020) \
|| defined (__mc68030__) || defined (mc68030) \
|| defined (__mc68040__) || defined (mc68040) \
|| defined (__mcpu32__) || defined (mcpu32) \
|| defined (__NeXT__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
: "=d" (w0), "=d" (w1) \
: "%0" ((USItype)(u)), "dmi" ((USItype)(v)))
#define UMUL_TIME 45
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divu%.l %4,%1:%0" \
: "=d" (q), "=d" (r) \
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d)))
#define UDIV_TIME 90
#define sdiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divs%.l %4,%1:%0" \
: "=d" (q), "=d" (r) \
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d)))
#else #define umul_ppmm(xh, xl, a, b) \
do { USItype __umul_tmp1, __umul_tmp2; \
__asm__ ("| Inlined umul_ppmm\n" \
" move%.l %5,%3\n" \
" move%.l %2,%0\n" \
" move%.w %3,%1\n" \
" swap %3\n" \
" swap %0\n" \
" mulu%.w %2,%1\n" \
" mulu%.w %3,%0\n" \
" mulu%.w %2,%3\n" \
" swap %2\n" \
" mulu%.w %5,%2\n" \
" add%.l %3,%2\n" \
" jcc 1f\n" \
" add%.l %#0x10000,%0\n" \
"1: move%.l %2,%3\n" \
" clr%.w %2\n" \
" swap %2\n" \
" swap %3\n" \
" clr%.w %3\n" \
" add%.l %3,%1\n" \
" addx%.l %2,%0\n" \
" | End inlined umul_ppmm" \
: "=&d" (xh), "=&d" (xl), \
"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
: "%2" ((USItype)(a)), "d" ((USItype)(b))); \
} while (0)
#define UMUL_TIME 100
#define UDIV_TIME 400
#endif #if (defined (__mc68020__) || defined (mc68020) \
|| defined (__mc68030__) || defined (mc68030) \
|| defined (__mc68040__) || defined (mc68040) \
|| defined (__mc68060__) || defined (mc68060) \
|| defined (__NeXT__)) \
&& ! defined (__mcpu32__)
#define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
: "=d" (count) \
: "od" ((USItype) (x)), "n" (0))
#define COUNT_LEADING_ZEROS_0 32
#endif
#endif
#if defined (__m88000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rJ" (bh), "%rJ" (al), "rJ" (bl))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rJ" (bh), "rJ" (al), "rJ" (bl))
#define count_leading_zeros(count, x) \
do { \
USItype __cbtmp; \
__asm__ ("ff1 %0,%1" : "=r" (__cbtmp) : "r" (x)); \
(count) = __cbtmp ^ 31; \
} while (0)
#define COUNT_LEADING_ZEROS_0 63 #if defined (__m88110__)
#define umul_ppmm(wh, wl, u, v) \
do { \
union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("mulu.d %0,%1,%2" : "=r" (__x.__ll) : "r" (u), "r" (v)); \
(wh) = __x.__i.__h; \
(wl) = __x.__i.__l; \
} while (0)
#define udiv_qrnnd(q, r, n1, n0, d) \
({union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x, __q; \
__x.__i.__h = (n1); __x.__i.__l = (n0); \
__asm__ ("divu.d %0,%1,%2" \
: "=r" (__q.__ll) : "r" (__x.__ll), "r" (d)); \
(r) = (n0) - __q.__l * (d); (q) = __q.__l; })
#define UMUL_TIME 5
#define UDIV_TIME 25
#else
#define UMUL_TIME 17
#define UDIV_TIME 150
#endif #endif
#if defined (__mips) && W_TYPE_SIZE == 32
#if __GMP_GNUC_PREREQ (4,4)
#define umul_ppmm(w1, w0, u, v) \
do { \
UDItype __ll = (UDItype)(u) * (v); \
w1 = __ll >> 32; \
w0 = __ll; \
} while (0)
#endif
#if !defined (umul_ppmm) && __GMP_GNUC_PREREQ (2,7)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("multu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
#endif
#if !defined (umul_ppmm)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("multu %2,%3\n\tmflo %0\n\tmfhi %1" \
: "=d" (w0), "=d" (w1) : "d" (u), "d" (v))
#endif
#define UMUL_TIME 10
#define UDIV_TIME 100
#endif
#if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64
#if __GMP_GNUC_PREREQ (4,4)
#define umul_ppmm(w1, w0, u, v) \
do { \
typedef unsigned int __ll_UTItype __attribute__((mode(TI))); \
__ll_UTItype __ll = (__ll_UTItype)(u) * (v); \
w1 = __ll >> 64; \
w0 = __ll; \
} while (0)
#endif
#if !defined (umul_ppmm) && __GMP_GNUC_PREREQ (2,7)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("dmultu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
#endif
#if !defined (umul_ppmm)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("dmultu %2,%3\n\tmflo %0\n\tmfhi %1" \
: "=d" (w0), "=d" (w1) : "d" (u), "d" (v))
#endif
#define UMUL_TIME 20
#define UDIV_TIME 140
#endif
#if defined (__mmix__) && W_TYPE_SIZE == 64
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("MULU %0,%2,%3" : "=r" (w0), "=z" (w1) : "r" (u), "r" (v))
#endif
#if defined (__ns32000__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __x; \
__asm__ ("meid %2,%0" \
: "=g" (__x.__ll) \
: "%0" ((USItype)(u)), "g" ((USItype)(v))); \
(w1) = __x.__i.__h; (w0) = __x.__i.__l;})
#define __umulsidi3(u, v) \
({UDItype __w; \
__asm__ ("meid %2,%0" \
: "=g" (__w) \
: "%0" ((USItype)(u)), "g" ((USItype)(v))); \
__w; })
#define udiv_qrnnd(q, r, n1, n0, d) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __x; \
__x.__i.__h = (n1); __x.__i.__l = (n0); \
__asm__ ("deid %2,%0" \
: "=g" (__x.__ll) \
: "0" (__x.__ll), "g" ((USItype)(d))); \
(r) = __x.__i.__l; (q) = __x.__i.__h; })
#define count_trailing_zeros(count,x) \
do { \
__asm__ ("ffsd %2,%0" \
: "=r" (count) \
: "0" ((USItype) 0), "r" ((USItype) (x))); \
} while (0)
#endif
#if (HAVE_HOST_CPU_FAMILY_power || HAVE_HOST_CPU_FAMILY_powerpc) \
&& W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl)); \
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl)); \
else \
__asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
#define count_leading_zeros(count, x) \
__asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 32
#if HAVE_HOST_CPU_FAMILY_powerpc
#if __GMP_GNUC_PREREQ (4,4)
#define umul_ppmm(w1, w0, u, v) \
do { \
UDItype __ll = (UDItype)(u) * (v); \
w1 = __ll >> 32; \
w0 = __ll; \
} while (0)
#endif
#if !defined (umul_ppmm)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#endif
#define UMUL_TIME 15
#define smul_ppmm(ph, pl, m0, m1) \
do { \
SItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define SMUL_TIME 14
#define UDIV_TIME 120
#else
#define UMUL_TIME 8
#define smul_ppmm(xh, xl, m0, m1) \
__asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
#define SMUL_TIME 4
#define sdiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
#define UDIV_TIME 100
#endif
#endif
#if HAVE_HOST_CPU_FAMILY_powerpc && W_TYPE_SIZE == 64
#if !defined (_LONG_LONG_LIMB)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl)); \
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl)); \
else \
__asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bl) && bl > -0x8000 && bl <= 0x8000) { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("addic %1,%3,%4\n\tsubfze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "*rI" (-bl)); \
else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
__asm__ ("addic %1,%3,%4\n\tsubfme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "*rI" (-bl)); \
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("addic %1,%3,%4\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "*rI" (-bl)); \
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("addic %1,%3,%4\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "*rI" (-bl)); \
else \
__asm__ ("addic %1,%4,%5\n\tsubfe %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "*rI" (-bl)); \
} else { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl)); \
else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl)); \
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl)); \
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl)); \
else \
__asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} \
} while (0)
#endif #define count_leading_zeros(count, x) \
__asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 64
#if 0#endif
#if !defined (umul_ppmm)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#endif
#define UMUL_TIME 15
#define smul_ppmm(ph, pl, m0, m1) \
do { \
DItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define SMUL_TIME 14 #define UDIV_TIME 120 #endif
#if defined (__pyr__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addw %5,%1\n\taddwc %3,%0" \
: "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subw %5,%1\n\tsubwb %3,%0" \
: "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("movw %1,%R0\n\tuemul %2,%0" \
: "=&r" (__x.__ll) \
: "g" ((USItype) (u)), "g" ((USItype)(v))); \
(w1) = __x.__i.__h; (w0) = __x.__i.__l;})
#endif
#if defined (__ibm032__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("a %1,%5\n\tae %0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "r" ((USItype)(bh)), \
"%1" ((USItype)(al)), "r" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("s %1,%5\n\tse %0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((USItype)(ah)), "r" ((USItype)(bh)), \
"1" ((USItype)(al)), "r" ((USItype)(bl)))
#define smul_ppmm(ph, pl, m0, m1) \
__asm__ ( \
"s r2,r2\n" \
" mts r10,%2\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" cas %0,r2,r0\n" \
" mfs r10,%1" \
: "=r" (ph), "=r" (pl) \
: "%r" ((USItype)(m0)), "r" ((USItype)(m1)) \
: "r2")
#define UMUL_TIME 20
#define UDIV_TIME 200
#define count_leading_zeros(count, x) \
do { \
if ((x) >= 0x10000) \
__asm__ ("clz %0,%1" \
: "=r" (count) : "r" ((USItype)(x) >> 16)); \
else \
{ \
__asm__ ("clz %0,%1" \
: "=r" (count) : "r" ((USItype)(x))); \
(count) += 16; \
} \
} while (0)
#endif
#if (defined (__SH2__) || defined (__SH3__) || defined (__SH4__)) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
: "=r" (w1), "=r" (w0) : "r" (u), "r" (v) : "macl", "mach")
#define UMUL_TIME 5
#endif
#if defined (__sparc__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rI" (bh),"%rJ" (al), "rI" (bl) \
__CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl) \
__CLOBBER_CC)
FIXME#if defined (__sparc_v9__) || defined (__sparcv9)
#if 0
#else
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
#endif
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
USItype __q; \
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \
(r) = (n0) - __q * (d); \
(q) = __q; \
} while (0)
#else
#if defined (__sparc_v8__) \
|| defined (__sparcv8) \
|| HAVE_HOST_CPU_supersparc
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
#define UMUL_TIME 5
#if HAVE_HOST_CPU_supersparc
#define UDIV_TIME 60 #else
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
USItype __q; \
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \
(r) = (n0) - __q * (d); \
(q) = __q; \
} while (0)
#define UDIV_TIME 25
#endif
#else #if defined (__sparclite__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
#define UMUL_TIME 5
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd\n" \
" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
" tst %%g0\n" \
" divscc %3,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%0\n" \
" rd %%y,%1\n" \
" bl,a 1f\n" \
" add %1,%4,%1\n" \
"1: ! End of inline udiv_qrnnd" \
: "=r" (q), "=r" (r) : "r" (n1), "r" (n0), "rI" (d) \
: "%g1" __AND_CLOBBER_CC)
#define UDIV_TIME 37
#define count_leading_zeros(count, x) \
__asm__ ("scan %1,1,%0" : "=r" (count) : "r" (x))
#endif #endif #endif #ifndef umul_ppmm
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("! Inlined umul_ppmm\n" \
" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
" sra %3,31,%%g2 ! Don't move this insn\n" \
" and %2,%%g2,%%g2 ! Don't move this insn\n" \
" andcc %%g0,0,%%g1 ! Don't move this insn\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,0,%%g1\n" \
" add %%g1,%%g2,%0\n" \
" rd %%y,%1" \
: "=r" (w1), "=r" (w0) : "%rI" (u), "r" (v) \
: "%g1", "%g2" __AND_CLOBBER_CC)
#define UMUL_TIME 39 #endif
#ifndef udiv_qrnnd
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UWtype __r; \
(q) = __MPN(udiv_qrnnd) (&__r, (n1), (n0), (d)); \
(r) = __r; \
} while (0)
extern UWtype __MPN(udiv_qrnnd) (UWtype *, UWtype, UWtype, UWtype);
#ifndef UDIV_TIME
#define UDIV_TIME 140
#endif
#endif #endif #endif
#if defined (__sparc__) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ( \
"addcc %r4,%5,%1\n" \
" addccc %r6,%7,%%g0\n" \
" addc %r2,%3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rI" (bh), "%rJ" (al), "rI" (bl), \
"%rJ" ((al) >> 32), "rI" ((bl) >> 32) \
__CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ( \
"subcc %r4,%5,%1\n" \
" subccc %r6,%7,%%g0\n" \
" subc %r2,%3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl), \
"rJ" ((al) >> 32), "rI" ((bl) >> 32) \
__CLOBBER_CC)
#if __VIS__ >= 0x300
#undef add_ssaaaa
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ( \
"addcc %r4, %5, %1\n" \
" addxc %r2, %r3, %0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rJ" (bh), "%rJ" (al), "rI" (bl) __CLOBBER_CC)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
(pl) = __m0 * __m1; \
__asm__ ("umulxhi\t%2, %1, %0" \
: "=r" (ph) \
: "%r" (__m0), "r" (__m1)); \
} while (0)
#define count_leading_zeros(count, x) \
__asm__ ("lzd\t%1,%0" : "=r" (count) : "r" (x))
#endif
#endif
#if (defined (__vax) || defined (__vax__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
: "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
: "=g" (sh), "=&g" (sl) \
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
"1" ((USItype)(al)), "g" ((USItype)(bl)))
#define smul_ppmm(xh, xl, m0, m1) \
do { \
union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __x; \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("emul %1,%2,$0,%0" \
: "=g" (__x.__ll) : "g" (__m0), "g" (__m1)); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0)
#define sdiv_qrnnd(q, r, n1, n0, d) \
do { \
union {DItype __ll; \
struct {SItype __l, __h;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("ediv %3,%2,%0,%1" \
: "=g" (q), "=g" (r) : "g" (__x.__ll), "g" (d)); \
} while (0)
#if 0
#endif
#endif
#if defined (__z8000__) && W_TYPE_SIZE == 16
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((unsigned int)(ah)), "r" ((unsigned int)(bh)), \
"%1" ((unsigned int)(al)), "rQR" ((unsigned int)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((unsigned int)(ah)), "r" ((unsigned int)(bh)), \
"1" ((unsigned int)(al)), "rQR" ((unsigned int)(bl)))
#define umul_ppmm(xh, xl, m0, m1) \
do { \
union {long int __ll; \
struct {unsigned int __h, __l;} __i; \
} __x; \
unsigned int __m0 = (m0), __m1 = (m1); \
__asm__ ("mult %S0,%H3" \
: "=r" (__x.__i.__h), "=r" (__x.__i.__l) \
: "%1" (m0), "rQR" (m1)); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
(xh) += ((((signed int) __m0 >> 15) & __m1) \
+ (((signed int) __m1 >> 15) & __m0)); \
} while (0)
#endif
#endif
#endif
FIXME#if !defined (umul_ppmm) && defined (__umulsidi3)
#define umul_ppmm(ph, pl, m0, m1) \
{ \
UDWtype __ll = __umulsidi3 (m0, m1); \
ph = (UWtype) (__ll >> W_TYPE_SIZE); \
pl = (UWtype) __ll; \
}
#endif
#if !defined (__umulsidi3)
#define __umulsidi3(u, v) \
({UWtype __hi, __lo; \
umul_ppmm (__hi, __lo, u, v); \
((UDWtype) __hi << W_TYPE_SIZE) | __lo; })
#endif
#define mpn_umul_ppmm __MPN(umul_ppmm)
extern UWtype mpn_umul_ppmm (UWtype *, UWtype, UWtype);
#if ! defined (umul_ppmm) && HAVE_NATIVE_mpn_umul_ppmm \
&& ! defined (LONGLONG_STANDALONE)
#define umul_ppmm(wh, wl, u, v) \
do { \
UWtype __umul_ppmm__p0; \
(wh) = mpn_umul_ppmm (&__umul_ppmm__p0, (UWtype) (u), (UWtype) (v));\
(wl) = __umul_ppmm__p0; \
} while (0)
#endif
#define mpn_umul_ppmm_r __MPN(umul_ppmm_r)
extern UWtype mpn_umul_ppmm_r (UWtype, UWtype, UWtype *);
#if ! defined (umul_ppmm) && HAVE_NATIVE_mpn_umul_ppmm_r \
&& ! defined (LONGLONG_STANDALONE)
#define umul_ppmm(wh, wl, u, v) \
do { \
UWtype __umul_p0; \
(wh) = mpn_umul_ppmm_r ((UWtype) (u), (UWtype) (v), &__umul_p0); \
(wl) = __umul_p0; \
} while (0)
#endif
#define mpn_udiv_qrnnd __MPN(udiv_qrnnd)
extern UWtype mpn_udiv_qrnnd (UWtype *, UWtype, UWtype, UWtype);
#if ! defined (udiv_qrnnd) && HAVE_NATIVE_mpn_udiv_qrnnd \
&& ! defined (LONGLONG_STANDALONE)
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
UWtype __udiv_qrnnd_r; \
(q) = mpn_udiv_qrnnd (&__udiv_qrnnd_r, \
(UWtype) (n1), (UWtype) (n0), (UWtype) d); \
(r) = __udiv_qrnnd_r; \
} while (0)
#endif
#define mpn_udiv_qrnnd_r __MPN(udiv_qrnnd_r)
extern UWtype mpn_udiv_qrnnd_r (UWtype, UWtype, UWtype, UWtype *);
#if ! defined (udiv_qrnnd) && HAVE_NATIVE_mpn_udiv_qrnnd_r \
&& ! defined (LONGLONG_STANDALONE)
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
UWtype __udiv_qrnnd_r; \
(q) = mpn_udiv_qrnnd_r ((UWtype) (n1), (UWtype) (n0), (UWtype) d, \
&__udiv_qrnnd_r); \
(r) = __udiv_qrnnd_r; \
} while (0)
#endif
#if !defined (add_ssaaaa)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
UWtype __x; \
__x = (al) + (bl); \
(sh) = (ah) + (bh) + (__x < (al)); \
(sl) = __x; \
} while (0)
#endif
#if !defined (sub_ddmmss)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
UWtype __x; \
__x = (al) - (bl); \
(sh) = (ah) - (bh) - ((al) < (bl)); \
(sl) = __x; \
} while (0)
#endif
#if !defined (umul_ppmm) && defined (smul_ppmm)
#define umul_ppmm(w1, w0, u, v) \
do { \
UWtype __w1; \
UWtype __xm0 = (u), __xm1 = (v); \
smul_ppmm (__w1, w0, __xm0, __xm1); \
(w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
} while (0)
#endif
#if !defined (umul_ppmm)
#define umul_ppmm(w1, w0, u, v) \
do { \
UWtype __x0, __x1, __x2, __x3; \
UHWtype __ul, __vl, __uh, __vh; \
UWtype __u = (u), __v = (v); \
\
__ul = __ll_lowpart (__u); \
__uh = __ll_highpart (__u); \
__vl = __ll_lowpart (__v); \
__vh = __ll_highpart (__v); \
\
__x0 = (UWtype) __ul * __vl; \
__x1 = (UWtype) __ul * __vh; \
__x2 = (UWtype) __uh * __vl; \
__x3 = (UWtype) __uh * __vh; \
\
__x1 += __ll_highpart (__x0); \
__x1 += __x2; \
if (__x1 < __x2) \
__x3 += __ll_B; \
\
(w1) = __x3 + __ll_highpart (__x1); \
(w0) = (__x1 << W_TYPE_SIZE/2) + __ll_lowpart (__x0); \
} while (0)
#endif
#if !defined (smul_ppmm)
#define smul_ppmm(w1, w0, u, v) \
do { \
UWtype __w1; \
UWtype __xm0 = (u), __xm1 = (v); \
umul_ppmm (__w1, w0, __xm0, __xm1); \
(w1) = __w1 - (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
- (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
} while (0)
#endif
#define __udiv_qrnnd_c(q, r, n1, n0, d) \
do { \
UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
\
ASSERT ((d) != 0); \
ASSERT ((n1) < (d)); \
\
__d1 = __ll_highpart (d); \
__d0 = __ll_lowpart (d); \
\
__q1 = (n1) / __d1; \
__r1 = (n1) - __q1 * __d1; \
__m = __q1 * __d0; \
__r1 = __r1 * __ll_B | __ll_highpart (n0); \
if (__r1 < __m) \
{ \
__q1--, __r1 += (d); \
if (__r1 >= (d)) \
if (__r1 < __m) \
__q1--, __r1 += (d); \
} \
__r1 -= __m; \
\
__q0 = __r1 / __d1; \
__r0 = __r1 - __q0 * __d1; \
__m = __q0 * __d0; \
__r0 = __r0 * __ll_B | __ll_lowpart (n0); \
if (__r0 < __m) \
{ \
__q0--, __r0 += (d); \
if (__r0 >= (d)) \
if (__r0 < __m) \
__q0--, __r0 += (d); \
} \
__r0 -= __m; \
\
(q) = __q1 * __ll_B | __q0; \
(r) = __r0; \
} while (0)
#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
#define udiv_qrnnd(q, r, nh, nl, d) \
do { \
UWtype __r; \
(q) = __MPN(udiv_w_sdiv) (&__r, nh, nl, d); \
(r) = __r; \
} while (0)
__GMP_DECLSPEC UWtype __MPN(udiv_w_sdiv) (UWtype *, UWtype, UWtype, UWtype);
#endif
#if !defined (udiv_qrnnd)
#define UDIV_NEEDS_NORMALIZATION 1
#define udiv_qrnnd __udiv_qrnnd_c
#endif
#if !defined (count_leading_zeros)
#define count_leading_zeros(count, x) \
do { \
UWtype __xr = (x); \
UWtype __a; \
\
if (W_TYPE_SIZE == 32) \
{ \
__a = __xr < ((UWtype) 1 << 2*__BITS4) \
? (__xr < ((UWtype) 1 << __BITS4) ? 1 : __BITS4 + 1) \
: (__xr < ((UWtype) 1 << 3*__BITS4) ? 2*__BITS4 + 1 \
: 3*__BITS4 + 1); \
} \
else \
{ \
for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
if (((__xr >> __a) & 0xff) != 0) \
break; \
++__a; \
} \
\
(count) = W_TYPE_SIZE + 1 - __a - __clz_tab[__xr >> __a]; \
} while (0)
#define COUNT_LEADING_ZEROS_0 (W_TYPE_SIZE - 1)
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
#define COUNT_LEADING_ZEROS_SLOW
#endif
#if HAVE_HOST_CPU_FAMILY_x86 && WANT_FAT_BINARY
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
#endif
#ifdef COUNT_LEADING_ZEROS_NEED_CLZ_TAB
extern const unsigned char __GMP_DECLSPEC __clz_tab[129];
#endif
#if !defined (count_trailing_zeros)
#if !defined (COUNT_LEADING_ZEROS_SLOW)
#define count_trailing_zeros(count, x) \
do { \
UWtype __ctz_x = (x); \
UWtype __ctz_c; \
ASSERT (__ctz_x != 0); \
count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
(count) = W_TYPE_SIZE - 1 - __ctz_c; \
} while (0)
#else
#define count_trailing_zeros(count, x) \
do { \
UWtype __ctz_x = (x); \
int __ctz_c; \
\
if (LIKELY ((__ctz_x & 0xff) != 0)) \
(count) = __clz_tab[__ctz_x & -__ctz_x] - 2; \
else \
{ \
for (__ctz_c = 8 - 2; __ctz_c < W_TYPE_SIZE - 2; __ctz_c += 8) \
{ \
__ctz_x >>= 8; \
if (LIKELY ((__ctz_x & 0xff) != 0)) \
break; \
} \
\
(count) = __ctz_c + __clz_tab[__ctz_x & -__ctz_x]; \
} \
} while (0)
#endif
#endif
#ifndef UDIV_NEEDS_NORMALIZATION
#define UDIV_NEEDS_NORMALIZATION 0
#endif
#ifndef UDIV_PREINV_ALWAYS
#define UDIV_PREINV_ALWAYS 0
#endif
#ifndef UMUL_TIME
#define UMUL_TIME 1
#endif
#ifndef UDIV_TIME
#define UDIV_TIME UMUL_TIME
#endif