src/os/unix/ngx_gcc_atomic_x86.h - nginx-1.7.10

Functions defined

Macros defined

Source code


  1. /*
  2. * Copyright (C) Igor Sysoev
  3. * Copyright (C) Nginx, Inc.
  4. */


  5. #if (NGX_SMP)
  6. #define NGX_SMP_LOCK  "lock;"
  7. #else
  8. #define NGX_SMP_LOCK
  9. #endif


  10. /*
  11. * "cmpxchgl  r, [m]":
  12. *
  13. *     if (eax == [m]) {
  14. *         zf = 1;
  15. *         [m] = r;
  16. *     } else {
  17. *         zf = 0;
  18. *         eax = [m];
  19. *     }
  20. *
  21. *
  22. * The "r" means the general register.
  23. * The "=a" and "a" are the %eax register.
  24. * Although we can return result in any register, we use "a" because it is
  25. * used in cmpxchgl anyway.  The result is actually in %al but not in %eax,
  26. * however, as the code is inlined gcc can test %al as well as %eax,
  27. * and icc adds "movzbl %al, %eax" by itself.
  28. *
  29. * The "cc" means that flags were changed.
  30. */

  31. static ngx_inline ngx_atomic_uint_t
  32. ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
  33.     ngx_atomic_uint_t set)
  34. {
  35.     u_char  res;

  36.     __asm__ volatile (

  37.          NGX_SMP_LOCK
  38.     "    cmpxchgl  %3, %1;   "
  39.     "    sete      %0;       "

  40.     : "=a" (res) : "m" (*lock), "a" (old), "r" (set) : "cc", "memory");

  41.     return res;
  42. }


  43. /*
  44. * "xaddl  r, [m]":
  45. *
  46. *     temp = [m];
  47. *     [m] += r;
  48. *     r = temp;
  49. *
  50. *
  51. * The "+r" means the general register.
  52. * The "cc" means that flags were changed.
  53. */


  54. #if !(( __GNUC__ == 2 && __GNUC_MINOR__ <= 7 ) || ( __INTEL_COMPILER >= 800 ))

  55. /*
  56. * icc 8.1 and 9.0 compile broken code with -march=pentium4 option:
  57. * ngx_atomic_fetch_add() always return the input "add" value,
  58. * so we use the gcc 2.7 version.
  59. *
  60. * icc 8.1 and 9.0 with -march=pentiumpro option or icc 7.1 compile
  61. * correct code.
  62. */

  63. static ngx_inline ngx_atomic_int_t
  64. ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
  65. {
  66.     __asm__ volatile (

  67.          NGX_SMP_LOCK
  68.     "    xaddl  %0, %1;   "

  69.     : "+r" (add) : "m" (*value) : "cc", "memory");

  70.     return add;
  71. }


  72. #else

  73. /*
  74. * gcc 2.7 does not support "+r", so we have to use the fixed
  75. * %eax ("=a" and "a") and this adds two superfluous instructions in the end
  76. * of code, something like this: "mov %eax, %edx / mov %edx, %eax".
  77. */

  78. static ngx_inline ngx_atomic_int_t
  79. ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
  80. {
  81.     ngx_atomic_uint_t  old;

  82.     __asm__ volatile (

  83.          NGX_SMP_LOCK
  84.     "    xaddl  %2, %1;   "

  85.     : "=a" (old) : "m" (*value), "a" (add) : "cc", "memory");

  86.     return old;
  87. }

  88. #endif


  89. /*
  90. * on x86 the write operations go in a program order, so we need only
  91. * to disable the gcc reorder optimizations
  92. */

  93. #define ngx_memory_barrier()    __asm__ volatile ("" ::: "memory")

  94. /* old "as" does not support "pause" opcode */
  95. #define ngx_cpu_pause()         __asm__ (".byte 0xf3, 0x90")