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src/core/ngx_cpuinfo.c - nginx-1.7.10

Functions defined

Source code


  2. /*
  3. * Copyright (C) Igor Sysoev
  4. * Copyright (C) Nginx, Inc.
  5. */


  8. #include <ngx_config.h>
  9. #include <ngx_core.h>


  12. #if (( __i386__ || __amd64__ ) && ( __GNUC__ || __INTEL_COMPILER ))


  15. static ngx_inline void ngx_cpuid(uint32_t i, uint32_t *buf);


  18. #if ( __i386__ )

  20. static ngx_inline void
  21. ‌ngx_cpuid(uint32_t i, uint32_t *buf)
  22. {

  24.     /*
  25.      * we could not use %ebx as output parameter if gcc builds PIC,
  26.      * and we could not save %ebx on stack, because %esp is used,
  27.      * when the -fomit-frame-pointer optimization is specified.
  28.      */

  30.     __asm__ (

  32.     "    mov    %%ebx, %%esi;  "

  34.     "    cpuid;                "
  35.     "    mov    %%eax, (%1);   "
  36.     "    mov    %%ebx, 4(%1);  "
  37.     "    mov    %%edx, 8(%1);  "
  38.     "    mov    %%ecx, 12(%1); "

  40.     "    mov    %%esi, %%ebx;  "

  42.     : : "a" (i), "D" (buf) : "ecx", "edx", "esi", "memory" );
  43. }


  46. #else /* __amd64__ */


  49. static ngx_inline void
  50. ‌ngx_cpuid(uint32_t i, uint32_t *buf)
  51. {
  52.     uint32_t  eax, ebx, ecx, edx;

  54.     __asm__ (

  56.         "cpuid"

  58.     : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) : "a" (i) );

  60.     buf[0] = eax;
  61.     buf[1] = ebx;
  62.     buf[2] = edx;
  63.     buf[3] = ecx;
  64. }


  67. #endif


  70. /* auto detect the L2 cache line size of modern and widespread CPUs */

  72. void
  73. ‌ngx_cpuinfo(void)
  74. {
  75.     u_char    *vendor;
  76.     uint32_t   vbuf[5], cpu[4], model;

  78.     vbuf[0] = 0;
  79.     vbuf[1] = 0;
  80.     vbuf[2] = 0;
  81.     vbuf[3] = 0;
  82.     vbuf[4] = 0;

  84.     ngx_cpuid(0, vbuf);

  86.     vendor = (u_char *) &vbuf[1];

  88.     if (vbuf[0] == 0) {
  89.         return;
  90.     }

  92.     ngx_cpuid(1, cpu);

  94.     if (ngx_strcmp(vendor, "GenuineIntel") == 0) {

  96.         switch ((cpu[0] & 0xf00) >> 8) {

  98.         /* Pentium */
  99.         case 5:
  100.             ngx_cacheline_size = 32;
  101.             break;

  103.         /* Pentium Pro, II, III */
  104.         case 6:
  105.             ngx_cacheline_size = 32;

  107.             model = ((cpu[0] & 0xf0000) >> 8) | (cpu[0] & 0xf0);

  109.             if (model >= 0xd0) {
  110.                 /* Intel Core, Core 2, Atom */
  111.                 ngx_cacheline_size = 64;
  112.             }

  114.             break;

  116.         /*
  117.          * Pentium 4, although its cache line size is 64 bytes,
  118.          * it prefetches up to two cache lines during memory read
  119.          */
  120.         case 15:
  121.             ngx_cacheline_size = 128;
  122.             break;
  123.         }

  125.     } else if (ngx_strcmp(vendor, "AuthenticAMD") == 0) {
  126.         ngx_cacheline_size = 64;
  127.     }
  128. }

  130. #else


  133. void
  134. ‌ngx_cpuinfo(void)
  135. {
  136. }


  139. #endif

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