gdb/frv-tdep.c - gdb

Global variables defined

Data types defined

Functions defined

Source code

  1. /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.

  3.    Copyright (C) 2002-2015 Free Software Foundation, Inc.

  5.    This file is part of GDB.

  7.    This program is free software; you can redistribute it and/or modify
  8.    it under the terms of the GNU General Public License as published by
  9.    the Free Software Foundation; either version 3 of the License, or
  10.    (at your option) any later version.

  12.    This program is distributed in the hope that it will be useful,
  13.    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.    GNU General Public License for more details.

  17.    You should have received a copy of the GNU General Public License
  18.    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

  20. #include "defs.h"
  21. #include "inferior.h"
  22. #include "gdbcore.h"
  23. #include "arch-utils.h"
  24. #include "regcache.h"
  25. #include "frame.h"
  26. #include "frame-unwind.h"
  27. #include "frame-base.h"
  28. #include "trad-frame.h"
  29. #include "dis-asm.h"
  30. #include "sim-regno.h"
  31. #include "gdb/sim-frv.h"
  32. #include "opcodes/frv-desc.h"        /* for the H_SPR_... enums */
  33. #include "symtab.h"
  34. #include "elf-bfd.h"
  35. #include "elf/frv.h"
  36. #include "osabi.h"
  37. #include "infcall.h"
  38. #include "solib.h"
  39. #include "frv-tdep.h"
  40. #include "objfiles.h"

  42. extern void _initialize_frv_tdep (void);

  44. ‌struct frv_unwind_cache                /* was struct frame_extra_info */
  45.   {
  46.     /* The previous frame's inner-most stack address.  Used as this
  47.        frame ID's stack_addr.  */
  48.     CORE_ADDR prev_sp;

  50.     /* The frame's base, optionally used by the high-level debug info.  */
  51.     CORE_ADDR base;

  53.     /* Table indicating the location of each and every register.  */
  54.     struct trad_frame_saved_reg *saved_regs;
  55.   };

  57. /* A structure describing a particular variant of the FRV.
  58.    We allocate and initialize one of these structures when we create
  59.    the gdbarch object for a variant.

  61.    At the moment, all the FR variants we support differ only in which
  62.    registers are present; the portable code of GDB knows that
  63.    registers whose names are the empty string don't exist, so the
  64.    `register_names' array captures all the per-variant information we
  65.    need.

  67.    in the future, if we need to have per-variant maps for raw size,
  68.    virtual type, etc., we should replace register_names with an array
  69.    of structures, each of which gives all the necessary info for one
  70.    register.  Don't stick parallel arrays in here --- that's so
  71.    Fortran.  */
  72. ‌struct gdbarch_tdep
  73. {
  74.   /* Which ABI is in use?  */
  75.   enum frv_abi frv_abi;

  77.   /* How many general-purpose registers does this variant have?  */
  78.   int num_gprs;

  80.   /* How many floating-point registers does this variant have?  */
  81.   int num_fprs;

  83.   /* How many hardware watchpoints can it support?  */
  84.   int num_hw_watchpoints;

  86.   /* How many hardware breakpoints can it support?  */
  87.   int num_hw_breakpoints;

  89.   /* Register names.  */
  90.   char **register_names;
  91. };

  93. /* Return the FR-V ABI associated with GDBARCH.  */
  94. enum frv_abi
  95. ‌frv_abi (struct gdbarch *gdbarch)
  96. {
  97.   return gdbarch_tdep (gdbarch)->frv_abi;
  98. }

  100. /* Fetch the interpreter and executable loadmap addresses (for shared
  101.    library support) for the FDPIC ABI.  Return 0 if successful, -1 if
  102.    not.  (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.)  */
  103. int
  104. ‌frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr,
  105.                              CORE_ADDR *exec_addr)
  106. {
  107.   if (frv_abi (gdbarch) != FRV_ABI_FDPIC)
  108.     return -1;
  109.   else
  110.     {
  111.       struct regcache *regcache = get_current_regcache ();

  113.       if (interp_addr != NULL)
  114.         {
  115.           ULONGEST val;
  116.           regcache_cooked_read_unsigned (regcache,
  117.                                          fdpic_loadmap_interp_regnum, &val);
  118.           *interp_addr = val;
  119.         }
  120.       if (exec_addr != NULL)
  121.         {
  122.           ULONGEST val;
  123.           regcache_cooked_read_unsigned (regcache,
  124.                                          fdpic_loadmap_exec_regnum, &val);
  125.           *exec_addr = val;
  126.         }
  127.       return 0;
  128.     }
  129. }

  131. /* Allocate a new variant structure, and set up default values for all
  132.    the fields.  */
  133. static struct gdbarch_tdep *
  134. ‌new_variant (void)
  135. {
  136.   struct gdbarch_tdep *var;
  137.   int r;

  139.   var = xmalloc (sizeof (*var));
  140.   memset (var, 0, sizeof (*var));

  142.   var->frv_abi = FRV_ABI_EABI;
  143.   var->num_gprs = 64;
  144.   var->num_fprs = 64;
  145.   var->num_hw_watchpoints = 0;
  146.   var->num_hw_breakpoints = 0;

  148.   /* By default, don't supply any general-purpose or floating-point
  149.      register names.  */
  150.   var->register_names
  151.     = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
  152.                          * sizeof (char *));
  153.   for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
  154.     var->register_names[r] = "";

  156.   /* Do, however, supply default names for the known special-purpose
  157.      registers.  */

  159.   var->register_names[pc_regnum] = "pc";
  160.   var->register_names[lr_regnum] = "lr";
  161.   var->register_names[lcr_regnum] = "lcr";

  163.   var->register_names[psr_regnum] = "psr";
  164.   var->register_names[ccr_regnum] = "ccr";
  165.   var->register_names[cccr_regnum] = "cccr";
  166.   var->register_names[tbr_regnum] = "tbr";

  168.   /* Debug registers.  */
  169.   var->register_names[brr_regnum] = "brr";
  170.   var->register_names[dbar0_regnum] = "dbar0";
  171.   var->register_names[dbar1_regnum] = "dbar1";
  172.   var->register_names[dbar2_regnum] = "dbar2";
  173.   var->register_names[dbar3_regnum] = "dbar3";

  175.   /* iacc0 (Only found on MB93405.)  */
  176.   var->register_names[iacc0h_regnum] = "iacc0h";
  177.   var->register_names[iacc0l_regnum] = "iacc0l";
  178.   var->register_names[iacc0_regnum] = "iacc0";

  180.   /* fsr0 (Found on FR555 and FR501.)  */
  181.   var->register_names[fsr0_regnum] = "fsr0";

  183.   /* acc0 - acc7.  The architecture provides for the possibility of many
  184.      more (up to 64 total), but we don't want to make that big of a hole
  185.      in the G packet.  If we need more in the future, we'll add them
  186.      elsewhere.  */
  187.   for (r = acc0_regnum; r <= acc7_regnum; r++)
  188.     {
  189.       char *buf;
  190.       buf = xstrprintf ("acc%d", r - acc0_regnum);
  191.       var->register_names[r] = buf;
  192.     }

  194.   /* accg0 - accg7: These are one byte registers.  The remote protocol
  195.      provides the raw values packed four into a slot.  accg0123 and
  196.      accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
  197.      We don't provide names for accg0123 and accg4567 since the user will
  198.      likely not want to see these raw values.  */

  200.   for (r = accg0_regnum; r <= accg7_regnum; r++)
  201.     {
  202.       char *buf;
  203.       buf = xstrprintf ("accg%d", r - accg0_regnum);
  204.       var->register_names[r] = buf;
  205.     }

  207.   /* msr0 and msr1.  */

  209.   var->register_names[msr0_regnum] = "msr0";
  210.   var->register_names[msr1_regnum] = "msr1";

  212.   /* gner and fner registers.  */
  213.   var->register_names[gner0_regnum] = "gner0";
  214.   var->register_names[gner1_regnum] = "gner1";
  215.   var->register_names[fner0_regnum] = "fner0";
  216.   var->register_names[fner1_regnum] = "fner1";

  218.   return var;
  219. }


  222. /* Indicate that the variant VAR has NUM_GPRS general-purpose
  223.    registers, and fill in the names array appropriately.  */
  224. static void
  225. ‌set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
  226. {
  227.   int r;

  229.   var->num_gprs = num_gprs;

  231.   for (r = 0; r < num_gprs; ++r)
  232.     {
  233.       char buf[20];

  235.       xsnprintf (buf, sizeof (buf), "gr%d", r);
  236.       var->register_names[first_gpr_regnum + r] = xstrdup (buf);
  237.     }
  238. }


  241. /* Indicate that the variant VAR has NUM_FPRS floating-point
  242.    registers, and fill in the names array appropriately.  */
  243. static void
  244. ‌set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
  245. {
  246.   int r;

  248.   var->num_fprs = num_fprs;

  250.   for (r = 0; r < num_fprs; ++r)
  251.     {
  252.       char buf[20];

  254.       xsnprintf (buf, sizeof (buf), "fr%d", r);
  255.       var->register_names[first_fpr_regnum + r] = xstrdup (buf);
  256.     }
  257. }

  259. static void
  260. ‌set_variant_abi_fdpic (struct gdbarch_tdep *var)
  261. {
  262.   var->frv_abi = FRV_ABI_FDPIC;
  263.   var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec");
  264.   var->register_names[fdpic_loadmap_interp_regnum]
  265.     = xstrdup ("loadmap_interp");
  266. }

  268. static void
  269. ‌set_variant_scratch_registers (struct gdbarch_tdep *var)
  270. {
  271.   var->register_names[scr0_regnum] = xstrdup ("scr0");
  272.   var->register_names[scr1_regnum] = xstrdup ("scr1");
  273.   var->register_names[scr2_regnum] = xstrdup ("scr2");
  274.   var->register_names[scr3_regnum] = xstrdup ("scr3");
  275. }

  277. static const char *
  278. ‌frv_register_name (struct gdbarch *gdbarch, int reg)
  279. {
  280.   if (reg < 0)
  281.     return "?toosmall?";
  282.   if (reg >= frv_num_regs + frv_num_pseudo_regs)
  283.     return "?toolarge?";

  285.   return gdbarch_tdep (gdbarch)->register_names[reg];
  286. }


  289. static struct type *
  290. ‌frv_register_type (struct gdbarch *gdbarch, int reg)
  291. {
  292.   if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
  293.     return builtin_type (gdbarch)->builtin_float;
  294.   else if (reg == iacc0_regnum)
  295.     return builtin_type (gdbarch)->builtin_int64;
  296.   else
  297.     return builtin_type (gdbarch)->builtin_int32;
  298. }

  300. static enum register_status
  301. ‌frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
  302.                           int reg, gdb_byte *buffer)
  303. {
  304.   enum register_status status;

  306.   if (reg == iacc0_regnum)
  307.     {
  308.       status = regcache_raw_read (regcache, iacc0h_regnum, buffer);
  309.       if (status == REG_VALID)
  310.         status = regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
  311.     }
  312.   else if (accg0_regnum <= reg && reg <= accg7_regnum)
  313.     {
  314.       /* The accg raw registers have four values in each slot with the
  315.          lowest register number occupying the first byte.  */

  317.       int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
  318.       int byte_num = (reg - accg0_regnum) % 4;
  319.       gdb_byte buf[4];

  321.       status = regcache_raw_read (regcache, raw_regnum, buf);
  322.       if (status == REG_VALID)
  323.         {
  324.           memset (buffer, 0, 4);
  325.           /* FR-V is big endian, so put the requested byte in the
  326.              first byte of the buffer allocated to hold the
  327.              pseudo-register.  */
  328.           buffer[0] = buf[byte_num];
  329.         }
  330.     }
  331.   else
  332.     gdb_assert_not_reached ("invalid pseudo register number");

  334.   return status;
  335. }

  337. static void
  338. ‌frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
  339.                           int reg, const gdb_byte *buffer)
  340. {
  341.   if (reg == iacc0_regnum)
  342.     {
  343.       regcache_raw_write (regcache, iacc0h_regnum, buffer);
  344.       regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
  345.     }
  346.   else if (accg0_regnum <= reg && reg <= accg7_regnum)
  347.     {
  348.       /* The accg raw registers have four values in each slot with the
  349.          lowest register number occupying the first byte.  */

  351.       int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
  352.       int byte_num = (reg - accg0_regnum) % 4;
  353.       gdb_byte buf[4];

  355.       regcache_raw_read (regcache, raw_regnum, buf);
  356.       buf[byte_num] = ((bfd_byte *) buffer)[0];
  357.       regcache_raw_write (regcache, raw_regnum, buf);
  358.     }
  359. }

  361. static int
  362. ‌frv_register_sim_regno (struct gdbarch *gdbarch, int reg)
  363. {
  364.   static const int spr_map[] =
  365.     {
  366.       H_SPR_PSR,                /* psr_regnum */
  367.       H_SPR_CCR,                /* ccr_regnum */
  368.       H_SPR_CCCR,                /* cccr_regnum */
  369.       -1,                        /* fdpic_loadmap_exec_regnum */
  370.       -1,                        /* fdpic_loadmap_interp_regnum */
  371.       -1,                        /* 134 */
  372.       H_SPR_TBR,                /* tbr_regnum */
  373.       H_SPR_BRR,                /* brr_regnum */
  374.       H_SPR_DBAR0,                /* dbar0_regnum */
  375.       H_SPR_DBAR1,                /* dbar1_regnum */
  376.       H_SPR_DBAR2,                /* dbar2_regnum */
  377.       H_SPR_DBAR3,                /* dbar3_regnum */
  378.       H_SPR_SCR0,                /* scr0_regnum */
  379.       H_SPR_SCR1,                /* scr1_regnum */
  380.       H_SPR_SCR2,                /* scr2_regnum */
  381.       H_SPR_SCR3,                /* scr3_regnum */
  382.       H_SPR_LR,                        /* lr_regnum */
  383.       H_SPR_LCR,                /* lcr_regnum */
  384.       H_SPR_IACC0H,                /* iacc0h_regnum */
  385.       H_SPR_IACC0L,                /* iacc0l_regnum */
  386.       H_SPR_FSR0,                /* fsr0_regnum */
  387.       /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs.  */
  388.       -1,                        /* acc0_regnum */
  389.       -1,                        /* acc1_regnum */
  390.       -1,                        /* acc2_regnum */
  391.       -1,                        /* acc3_regnum */
  392.       -1,                        /* acc4_regnum */
  393.       -1,                        /* acc5_regnum */
  394.       -1,                        /* acc6_regnum */
  395.       -1,                        /* acc7_regnum */
  396.       -1,                        /* acc0123_regnum */
  397.       -1,                        /* acc4567_regnum */
  398.       H_SPR_MSR0,                /* msr0_regnum */
  399.       H_SPR_MSR1,                /* msr1_regnum */
  400.       H_SPR_GNER0,                /* gner0_regnum */
  401.       H_SPR_GNER1,                /* gner1_regnum */
  402.       H_SPR_FNER0,                /* fner0_regnum */
  403.       H_SPR_FNER1,                /* fner1_regnum */
  404.     };

  406.   gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));

  408.   if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
  409.     return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
  410.   else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
  411.     return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
  412.   else if (pc_regnum == reg)
  413.     return SIM_FRV_PC_REGNUM;
  414.   else if (reg >= first_spr_regnum
  415.            && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
  416.     {
  417.       int spr_reg_offset = spr_map[reg - first_spr_regnum];

  419.       if (spr_reg_offset < 0)
  420.         return SIM_REGNO_DOES_NOT_EXIST;
  421.       else
  422.         return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
  423.     }

  425.   internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg);
  426. }

  428. static const unsigned char *
  429. ‌frv_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenp)
  430. {
  431.   static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
  432.   *lenp = sizeof (breakpoint);
  433.   return breakpoint;
  434. }

  436. /* Define the maximum number of instructions which may be packed into a
  437.    bundle (VLIW instruction).  */
  438. ‌static const int max_instrs_per_bundle = 8;

  440. /* Define the size (in bytes) of an FR-V instruction.  */
  441. ‌static const int frv_instr_size = 4;

  443. /* Adjust a breakpoint's address to account for the FR-V architecture's
  444.    constraint that a break instruction must not appear as any but the
  445.    first instruction in the bundle.  */
  446. static CORE_ADDR
  447. ‌frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
  448. {
  449.   int count = max_instrs_per_bundle;
  450.   CORE_ADDR addr = bpaddr - frv_instr_size;
  451.   CORE_ADDR func_start = get_pc_function_start (bpaddr);

  453.   /* Find the end of the previous packing sequence.  This will be indicated
  454.      by either attempting to access some inaccessible memory or by finding
  455.      an instruction word whose packing bit is set to one.  */
  456.   while (count-- > 0 && addr >= func_start)
  457.     {
  458.       gdb_byte instr[frv_instr_size];
  459.       int status;

  461.       status = target_read_memory (addr, instr, sizeof instr);

  463.       if (status != 0)
  464.         break;

  466.       /* This is a big endian architecture, so byte zero will have most
  467.          significant byte.  The most significant bit of this byte is the
  468.          packing bit.  */
  469.       if (instr[0] & 0x80)
  470.         break;

  472.       addr -= frv_instr_size;
  473.     }

  475.   if (count > 0)
  476.     bpaddr = addr + frv_instr_size;

  478.   return bpaddr;
  479. }


  482. /* Return true if REG is a caller-saves ("scratch") register,
  483.    false otherwise.  */
  484. static int
  485. ‌is_caller_saves_reg (int reg)
  486. {
  487.   return ((4 <= reg && reg <= 7)
  488.           || (14 <= reg && reg <= 15)
  489.           || (32 <= reg && reg <= 47));
  490. }


  493. /* Return true if REG is a callee-saves register, false otherwise.  */
  494. static int
  495. ‌is_callee_saves_reg (int reg)
  496. {
  497.   return ((16 <= reg && reg <= 31)
  498.           || (48 <= reg && reg <= 63));
  499. }


  502. /* Return true if REG is an argument register, false otherwise.  */
  503. static int
  504. ‌is_argument_reg (int reg)
  505. {
  506.   return (8 <= reg && reg <= 13);
  507. }

  509. /* Scan an FR-V prologue, starting at PC, until frame->PC.
  510.    If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
  511.    We assume FRAME's saved_regs array has already been allocated and cleared.
  512.    Return the first PC value after the prologue.

  514.    Note that, for unoptimized code, we almost don't need this function
  515.    at all; all arguments and locals live on the stack, so we just need
  516.    the FP to find everything.  The catch: structures passed by value
  517.    have their addresses living in registers; they're never spilled to
  518.    the stack.  So if you ever want to be able to get to these
  519.    arguments in any frame but the top, you'll need to do this serious
  520.    prologue analysis.  */
  521. static CORE_ADDR
  522. ‌frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
  523.                       struct frame_info *this_frame,
  524.                       struct frv_unwind_cache *info)
  525. {
  526.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);

  528.   /* When writing out instruction bitpatterns, we use the following
  529.      letters to label instruction fields:
  530.      P - The parallel bit.  We don't use this.
  531.      J - The register number of GRj in the instruction description.
  532.      K - The register number of GRk in the instruction description.
  533.      I - The register number of GRi.
  534.      S - a signed imediate offset.
  535.      U - an unsigned immediate offset.

  537.      The dots below the numbers indicate where hex digit boundaries
  538.      fall, to make it easier to check the numbers.  */

  540.   /* Non-zero iff we've seen the instruction that initializes the
  541.      frame pointer for this function's frame.  */
  542.   int fp_set = 0;

  544.   /* If fp_set is non_zero, then this is the distance from
  545.      the stack pointer to frame pointer: fp = sp + fp_offset.  */
  546.   int fp_offset = 0;

  548.   /* Total size of frame prior to any alloca operations.  */
  549.   int framesize = 0;

  551.   /* Flag indicating if lr has been saved on the stack.  */
  552.   int lr_saved_on_stack = 0;

  554.   /* The number of the general-purpose register we saved the return
  555.      address ("link register") in, or -1 if we haven't moved it yet.  */
  556.   int lr_save_reg = -1;

  558.   /* Offset (from sp) at which lr has been saved on the stack.  */

  560.   int lr_sp_offset = 0;

  562.   /* If gr_saved[i] is non-zero, then we've noticed that general
  563.      register i has been saved at gr_sp_offset[i] from the stack
  564.      pointer.  */
  565.   char gr_saved[64];
  566.   int gr_sp_offset[64];

  568.   /* The address of the most recently scanned prologue instruction.  */
  569.   CORE_ADDR last_prologue_pc;

  571.   /* The address of the next instruction.  */
  572.   CORE_ADDR next_pc;

  574.   /* The upper bound to of the pc values to scan.  */
  575.   CORE_ADDR lim_pc;

  577.   memset (gr_saved, 0, sizeof (gr_saved));

  579.   last_prologue_pc = pc;

  581.   /* Try to compute an upper limit (on how far to scan) based on the
  582.      line number info.  */
  583.   lim_pc = skip_prologue_using_sal (gdbarch, pc);
  584.   /* If there's no line number info, lim_pc will be 0.  In that case,
  585.      set the limit to be 100 instructions away from pc.  Hopefully, this
  586.      will be far enough away to account for the entire prologue.  Don't
  587.      worry about overshooting the end of the function.  The scan loop
  588.      below contains some checks to avoid scanning unreasonably far.  */
  589.   if (lim_pc == 0)
  590.     lim_pc = pc + 400;

  592.   /* If we have a frame, we don't want to scan past the frame's pc.  This
  593.      will catch those cases where the pc is in the prologue.  */
  594.   if (this_frame)
  595.     {
  596.       CORE_ADDR frame_pc = get_frame_pc (this_frame);
  597.       if (frame_pc < lim_pc)
  598.         lim_pc = frame_pc;
  599.     }

  601.   /* Scan the prologue.  */
  602.   while (pc < lim_pc)
  603.     {
  604.       gdb_byte buf[frv_instr_size];
  605.       LONGEST op;

  607.       if (target_read_memory (pc, buf, sizeof buf) != 0)
  608.         break;
  609.       op = extract_signed_integer (buf, sizeof buf, byte_order);

  611.       next_pc = pc + 4;

  613.       /* The tests in this chain of ifs should be in order of
  614.          decreasing selectivity, so that more particular patterns get
  615.          to fire before less particular patterns.  */

  617.       /* Some sort of control transfer instruction: stop scanning prologue.
  618.          Integer Conditional Branch:
  619.           X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
  620.          Floating-point / media Conditional Branch:
  621.           X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
  622.          LCR Conditional Branch to LR
  623.           X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
  624.          Integer conditional Branches to LR
  625.           X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
  626.           X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
  627.          Floating-point/Media Branches to LR
  628.           X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
  629.           X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
  630.          Jump and Link
  631.           X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
  632.           X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
  633.          Call
  634.           X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
  635.          Return from Trap
  636.           X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
  637.          Integer Conditional Trap
  638.           X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
  639.           X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
  640.          Floating-point /media Conditional Trap
  641.           X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
  642.           X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
  643.          Break
  644.           X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
  645.          Media Trap
  646.           X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
  647.       if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
  648.           || (op & 0x01f80000) == 0x00300000  /* Jump and Link */
  649.           || (op & 0x01f80000) == 0x00100000  /* Return from Trap, Trap */
  650.           || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
  651.         {
  652.           /* Stop scanning; not in prologue any longer.  */
  653.           break;
  654.         }

  656.       /* Loading something from memory into fp probably means that
  657.          we're in the epilogue.  Stop scanning the prologue.
  658.          ld @(GRi, GRk), fp
  659.          X 000010 0000010 XXXXXX 000100 XXXXXX
  660.          ldi @(GRi, d12), fp
  661.          X 000010 0110010 XXXXXX XXXXXXXXXXXX */
  662.       else if ((op & 0x7ffc0fc0) == 0x04080100
  663.                || (op & 0x7ffc0000) == 0x04c80000)
  664.         {
  665.           break;
  666.         }

  668.       /* Setting the FP from the SP:
  669.          ori sp, 0, fp
  670.          P 000010 0100010 000001 000000000000 = 0x04881000
  671.          0 111111 1111111 111111 111111111111 = 0x7fffffff
  672.              .    .   .    .   .    .   .   .
  673.          We treat this as part of the prologue.  */
  674.       else if ((op & 0x7fffffff) == 0x04881000)
  675.         {
  676.           fp_set = 1;
  677.           fp_offset = 0;
  678.           last_prologue_pc = next_pc;
  679.         }

  681.       /* Move the link register to the scratch register grJ, before saving:
  682.          movsg lr, grJ
  683.          P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
  684.          0 111111 1111111 111111 111111 000000 = 0x7fffffc0
  685.              .    .   .    .   .    .    .   .
  686.          We treat this as part of the prologue.  */
  687.       else if ((op & 0x7fffffc0) == 0x080d01c0)
  688.         {
  689.           int gr_j = op & 0x3f;

  691.           /* If we're moving it to a scratch register, that's fine.  */
  692.           if (is_caller_saves_reg (gr_j))
  693.             {
  694.               lr_save_reg = gr_j;
  695.               last_prologue_pc = next_pc;
  696.             }
  697.         }

  699.       /* To save multiple callee-saves registers on the stack, at
  700.          offset zero:

  702.          std grK,@(sp,gr0)
  703.          P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
  704.          0 000000 1111111 111111 111111 111111 = 0x01ffffff

  706.          stq grK,@(sp,gr0)
  707.          P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
  708.          0 000000 1111111 111111 111111 111111 = 0x01ffffff
  709.              .    .   .    .   .    .    .   .
  710.          We treat this as part of the prologue, and record the register's
  711.          saved address in the frame structure.  */
  712.       else if ((op & 0x01ffffff) == 0x000c10c0
  713.             || (op & 0x01ffffff) == 0x000c1100)
  714.         {
  715.           int gr_k = ((op >> 25) & 0x3f);
  716.           int ope  = ((op >> 6)  & 0x3f);
  717.           int count;
  718.           int i;

  720.           /* Is it an std or an stq?  */
  721.           if (ope == 0x03)
  722.             count = 2;
  723.           else
  724.             count = 4;

  726.           /* Is it really a callee-saves register?  */
  727.           if (is_callee_saves_reg (gr_k))
  728.             {
  729.               for (i = 0; i < count; i++)
  730.                 {
  731.                   gr_saved[gr_k + i] = 1;
  732.                   gr_sp_offset[gr_k + i] = 4 * i;
  733.                 }
  734.               last_prologue_pc = next_pc;
  735.             }
  736.         }

  738.       /* Adjusting the stack pointer.  (The stack pointer is GR1.)
  739.          addi sp, S, sp
  740.          P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
  741.          0 111111 1111111 111111 000000000000 = 0x7ffff000
  742.              .    .   .    .   .    .   .   .
  743.          We treat this as part of the prologue.  */
  744.       else if ((op & 0x7ffff000) == 0x02401000)
  745.         {
  746.           if (framesize == 0)
  747.             {
  748.               /* Sign-extend the twelve-bit field.
  749.                  (Isn't there a better way to do this?)  */
  750.               int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;

  752.               framesize -= s;
  753.               last_prologue_pc = pc;
  754.             }
  755.           else
  756.             {
  757.               /* If the prologue is being adjusted again, we've
  758.                  likely gone too far; i.e. we're probably in the
  759.                  epilogue.  */
  760.               break;
  761.             }
  762.         }

  764.       /* Setting the FP to a constant distance from the SP:
  765.          addi sp, S, fp
  766.          P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
  767.          0 111111 1111111 111111 000000000000 = 0x7ffff000
  768.              .    .   .    .   .    .   .   .
  769.          We treat this as part of the prologue.  */
  770.       else if ((op & 0x7ffff000) == 0x04401000)
  771.         {
  772.           /* Sign-extend the twelve-bit field.
  773.              (Isn't there a better way to do this?)  */
  774.           int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
  775.           fp_set = 1;
  776.           fp_offset = s;
  777.           last_prologue_pc = pc;
  778.         }

  780.       /* To spill an argument register to a scratch register:
  781.             ori GRi, 0, GRk
  782.          P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
  783.          0 000000 1111111 000000 111111111111 = 0x01fc0fff
  784.              .    .   .    .   .    .   .   .
  785.          For the time being, we treat this as a prologue instruction,
  786.          assuming that GRi is an argument register.  This one's kind
  787.          of suspicious, because it seems like it could be part of a
  788.          legitimate body instruction.  But we only come here when the
  789.          source info wasn't helpful, so we have to do the best we can.
  790.          Hopefully once GCC and GDB agree on how to emit line number
  791.          info for prologues, then this code will never come into play.  */
  792.       else if ((op & 0x01fc0fff) == 0x00880000)
  793.         {
  794.           int gr_i = ((op >> 12) & 0x3f);

  796.           /* Make sure that the source is an arg register; if it is, we'll
  797.              treat it as a prologue instruction.  */
  798.           if (is_argument_reg (gr_i))
  799.             last_prologue_pc = next_pc;
  800.         }

  802.       /* To spill 16-bit values to the stack:
  803.              sthi GRk, @(fp, s)
  804.          P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
  805.          0 000000 1111111 111111 000000000000 = 0x01fff000
  806.              .    .   .    .   .    .   .   .
  807.          And for 8-bit values, we use STB instructions.
  808.              stbi GRk, @(fp, s)
  809.          P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
  810.          0 000000 1111111 111111 000000000000 = 0x01fff000
  811.              .    .   .    .   .    .   .   .
  812.          We check that GRk is really an argument register, and treat
  813.          all such as part of the prologue.  */
  814.       else if (   (op & 0x01fff000) == 0x01442000
  815.                || (op & 0x01fff000) == 0x01402000)
  816.         {
  817.           int gr_k = ((op >> 25) & 0x3f);

  819.           /* Make sure that GRk is really an argument register; treat
  820.              it as a prologue instruction if so.  */
  821.           if (is_argument_reg (gr_k))
  822.             last_prologue_pc = next_pc;
  823.         }

  825.       /* To save multiple callee-saves register on the stack, at a
  826.          non-zero offset:

  828.          stdi GRk, @(sp, s)
  829.          P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
  830.          0 000000 1111111 111111 000000000000 = 0x01fff000
  831.              .    .   .    .   .    .   .   .
  832.          stqi GRk, @(sp, s)
  833.          P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
  834.          0 000000 1111111 111111 000000000000 = 0x01fff000
  835.              .    .   .    .   .    .   .   .
  836.          We treat this as part of the prologue, and record the register's
  837.          saved address in the frame structure.  */
  838.       else if ((op & 0x01fff000) == 0x014c1000
  839.             || (op & 0x01fff000) == 0x01501000)
  840.         {
  841.           int gr_k = ((op >> 25) & 0x3f);
  842.           int count;
  843.           int i;

  845.           /* Is it a stdi or a stqi?  */
  846.           if ((op & 0x01fff000) == 0x014c1000)
  847.             count = 2;
  848.           else
  849.             count = 4;

  851.           /* Is it really a callee-saves register?  */
  852.           if (is_callee_saves_reg (gr_k))
  853.             {
  854.               /* Sign-extend the twelve-bit field.
  855.                  (Isn't there a better way to do this?)  */
  856.               int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;

  858.               for (i = 0; i < count; i++)
  859.                 {
  860.                   gr_saved[gr_k + i] = 1;
  861.                   gr_sp_offset[gr_k + i] = s + (4 * i);
  862.                 }
  863.               last_prologue_pc = next_pc;
  864.             }
  865.         }

  867.       /* Storing any kind of integer register at any constant offset
  868.          from any other register.

  870.          st GRk, @(GRi, gr0)
  871.          P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
  872.          0 000000 1111111 000000 111111 111111 = 0x01fc0fff
  873.              .    .   .    .   .    .    .   .
  874.          sti GRk, @(GRi, d12)
  875.          P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
  876.          0 000000 1111111 000000 000000000000 = 0x01fc0000
  877.              .    .   .    .   .    .   .   .
  878.          These could be almost anything, but a lot of prologue
  879.          instructions fall into this pattern, so let's decode the
  880.          instruction once, and then work at a higher level.  */
  881.       else if (((op & 0x01fc0fff) == 0x000c0080)
  882.             || ((op & 0x01fc0000) == 0x01480000))
  883.         {
  884.           int gr_k = ((op >> 25) & 0x3f);
  885.           int gr_i = ((op >> 12) & 0x3f);
  886.           int offset;

  888.           /* Are we storing with gr0 as an offset, or using an
  889.              immediate value?  */
  890.           if ((op & 0x01fc0fff) == 0x000c0080)
  891.             offset = 0;
  892.           else
  893.             offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;

  895.           /* If the address isn't relative to the SP or FP, it's not a
  896.              prologue instruction.  */
  897.           if (gr_i != sp_regnum && gr_i != fp_regnum)
  898.             {
  899.               /* Do nothing; not a prologue instruction.  */
  900.             }

  902.           /* Saving the old FP in the new frame (relative to the SP).  */
  903.           else if (gr_k == fp_regnum && gr_i == sp_regnum)
  904.             {
  905.               gr_saved[fp_regnum] = 1;
  906.               gr_sp_offset[fp_regnum] = offset;
  907.               last_prologue_pc = next_pc;
  908.             }

  910.           /* Saving callee-saves register(s) on the stack, relative to
  911.              the SP.  */
  912.           else if (gr_i == sp_regnum
  913.                    && is_callee_saves_reg (gr_k))
  914.             {
  915.               gr_saved[gr_k] = 1;
  916.               if (gr_i == sp_regnum)
  917.                 gr_sp_offset[gr_k] = offset;
  918.               else
  919.                 gr_sp_offset[gr_k] = offset + fp_offset;
  920.               last_prologue_pc = next_pc;
  921.             }

  923.           /* Saving the scratch register holding the return address.  */
  924.           else if (lr_save_reg != -1
  925.                    && gr_k == lr_save_reg)
  926.             {
  927.               lr_saved_on_stack = 1;
  928.               if (gr_i == sp_regnum)
  929.                 lr_sp_offset = offset;
  930.               else
  931.                 lr_sp_offset = offset + fp_offset;
  932.               last_prologue_pc = next_pc;
  933.             }

  935.           /* Spilling int-sized arguments to the stack.  */
  936.           else if (is_argument_reg (gr_k))
  937.             last_prologue_pc = next_pc;
  938.         }
  939.       pc = next_pc;
  940.     }

  942.   if (this_frame && info)
  943.     {
  944.       int i;
  945.       ULONGEST this_base;

  947.       /* If we know the relationship between the stack and frame
  948.          pointers, record the addresses of the registers we noticed.
  949.          Note that we have to do this as a separate step at the end,
  950.          because instructions may save relative to the SP, but we need
  951.          their addresses relative to the FP.  */
  952.       if (fp_set)
  953.         this_base = get_frame_register_unsigned (this_frame, fp_regnum);
  954.       else
  955.         this_base = get_frame_register_unsigned (this_frame, sp_regnum);

  957.       for (i = 0; i < 64; i++)
  958.         if (gr_saved[i])
  959.           info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];

  961.       info->prev_sp = this_base - fp_offset + framesize;
  962.       info->base = this_base;

  964.       /* If LR was saved on the stack, record its location.  */
  965.       if (lr_saved_on_stack)
  966.         info->saved_regs[lr_regnum].addr
  967.           = this_base - fp_offset + lr_sp_offset;

  969.       /* The call instruction moves the caller's PC in the callee's LR.
  970.          Since this is an unwind, do the reverse.  Copy the location of LR
  971.          into PC (the address / regnum) so that a request for PC will be
  972.          converted into a request for the LR.  */
  973.       info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];

  975.       /* Save the previous frame's computed SP value.  */
  976.       trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
  977.     }

  979.   return last_prologue_pc;
  980. }


  983. static CORE_ADDR
  984. ‌frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  985. {
  986.   CORE_ADDR func_addr, func_end, new_pc;

  988.   new_pc = pc;

  990.   /* If the line table has entry for a line *within* the function
  991.      (i.e., not in the prologue, and not past the end), then that's
  992.      our location.  */
  993.   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
  994.     {
  995.       struct symtab_and_line sal;

  997.       sal = find_pc_line (func_addr, 0);

  999.       if (sal.line != 0 && sal.end < func_end)
  1000.         {
  1001.           new_pc = sal.end;
  1002.         }
  1003.     }

  1005.   /* The FR-V prologue is at least five instructions long (twenty bytes).
  1006.      If we didn't find a real source location past that, then
  1007.      do a full analysis of the prologue.  */
  1008.   if (new_pc < pc + 20)
  1009.     new_pc = frv_analyze_prologue (gdbarch, pc, 0, 0);

  1011.   return new_pc;
  1012. }


  1015. /* Examine the instruction pointed to by PC.  If it corresponds to
  1016.    a call to __main, return the address of the next instruction.
  1017.    Otherwise, return PC.  */

  1019. static CORE_ADDR
  1020. ‌frv_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  1021. {
  1022.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1023.   gdb_byte buf[4];
  1024.   unsigned long op;
  1025.   CORE_ADDR orig_pc = pc;

  1027.   if (target_read_memory (pc, buf, 4))
  1028.     return pc;
  1029.   op = extract_unsigned_integer (buf, 4, byte_order);

  1031.   /* In PIC code, GR15 may be loaded from some offset off of FP prior
  1032.      to the call instruction.

  1034.      Skip over this instruction if present.  It won't be present in
  1035.      non-PIC code, and even in PIC code, it might not be present.
  1036.      (This is due to the fact that GR15, the FDPIC register, already
  1037.      contains the correct value.)

  1039.      The general form of the LDI is given first, followed by the
  1040.      specific instruction with the GRi and GRk filled in as FP and
  1041.      GR15.

  1043.      ldi @(GRi, d12), GRk
  1044.      P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
  1045.      0 000000 1111111 000000 000000000000 = 0x01fc0000
  1046.          .    .   .    .   .    .   .   .
  1047.      ldi @(FP, d12), GR15
  1048.      P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
  1049.      0 001111 1111111 000010 000000000000 = 0x7ffff000
  1050.          .    .   .    .   .    .   .   .               */

  1052.   if ((op & 0x7ffff000) == 0x1ec82000)
  1053.     {
  1054.       pc += 4;
  1055.       if (target_read_memory (pc, buf, 4))
  1056.         return orig_pc;
  1057.       op = extract_unsigned_integer (buf, 4, byte_order);
  1058.     }

  1060.   /* The format of an FRV CALL instruction is as follows:

  1062.      call label24
  1063.      P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
  1064.      0 000000 1111111 000000000000000000 = 0x01fc0000
  1065.          .    .   .    .   .   .   .   .

  1067.      where label24 is constructed by concatenating the H bits with the
  1068.      L bits.  The call target is PC + (4 * sign_ext(label24)).  */

  1070.   if ((op & 0x01fc0000) == 0x003c0000)
  1071.     {
  1072.       LONGEST displ;
  1073.       CORE_ADDR call_dest;
  1074.       struct bound_minimal_symbol s;

  1076.       displ = ((op & 0xfe000000) >> 7) | (op & 0x0003ffff);
  1077.       if ((displ & 0x00800000) != 0)
  1078.         displ |= ~((LONGEST) 0x00ffffff);

  1080.       call_dest = pc + 4 * displ;
  1081.       s = lookup_minimal_symbol_by_pc (call_dest);

  1083.       if (s.minsym != NULL
  1084.           && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
  1085.           && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0)
  1086.         {
  1087.           pc += 4;
  1088.           return pc;
  1089.         }
  1090.     }
  1091.   return orig_pc;
  1092. }


  1095. static struct frv_unwind_cache *
  1096. ‌frv_frame_unwind_cache (struct frame_info *this_frame,
  1097.                          void **this_prologue_cache)
  1098. {
  1099.   struct gdbarch *gdbarch = get_frame_arch (this_frame);
  1100.   struct frv_unwind_cache *info;

  1102.   if ((*this_prologue_cache))
  1103.     return (*this_prologue_cache);

  1105.   info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
  1106.   (*this_prologue_cache) = info;
  1107.   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);

  1109.   /* Prologue analysis does the rest...  */
  1110.   frv_analyze_prologue (gdbarch,
  1111.                         get_frame_func (this_frame), this_frame, info);

  1113.   return info;
  1114. }

  1116. static void
  1117. ‌frv_extract_return_value (struct type *type, struct regcache *regcache,
  1118.                           gdb_byte *valbuf)
  1119. {
  1120.   struct gdbarch *gdbarch = get_regcache_arch (regcache);
  1121.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1122.   int len = TYPE_LENGTH (type);

  1124.   if (len <= 4)
  1125.     {
  1126.       ULONGEST gpr8_val;
  1127.       regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
  1128.       store_unsigned_integer (valbuf, len, byte_order, gpr8_val);
  1129.     }
  1130.   else if (len == 8)
  1131.     {
  1132.       ULONGEST regval;

  1134.       regcache_cooked_read_unsigned (regcache, 8, &regval);
  1135.       store_unsigned_integer (valbuf, 4, byte_order, regval);
  1136.       regcache_cooked_read_unsigned (regcache, 9, &regval);
  1137.       store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, byte_order, regval);
  1138.     }
  1139.   else
  1140.     internal_error (__FILE__, __LINE__,
  1141.                     _("Illegal return value length: %d"), len);
  1142. }

  1144. static CORE_ADDR
  1145. ‌frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
  1146. {
  1147.   /* Require dword alignment.  */
  1148.   return align_down (sp, 8);
  1149. }

  1151. static CORE_ADDR
  1152. ‌find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point)
  1153. {
  1154.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1155.   CORE_ADDR descr;
  1156.   gdb_byte valbuf[4];
  1157.   CORE_ADDR start_addr;

  1159.   /* If we can't find the function in the symbol table, then we assume
  1160.      that the function address is already in descriptor form.  */
  1161.   if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL)
  1162.       || entry_point != start_addr)
  1163.     return entry_point;

  1165.   descr = frv_fdpic_find_canonical_descriptor (entry_point);

  1167.   if (descr != 0)
  1168.     return descr;

  1170.   /* Construct a non-canonical descriptor from space allocated on
  1171.      the stack.  */

  1173.   descr = value_as_long (value_allocate_space_in_inferior (8));
  1174.   store_unsigned_integer (valbuf, 4, byte_order, entry_point);
  1175.   write_memory (descr, valbuf, 4);
  1176.   store_unsigned_integer (valbuf, 4, byte_order,
  1177.                           frv_fdpic_find_global_pointer (entry_point));
  1178.   write_memory (descr + 4, valbuf, 4);
  1179.   return descr;
  1180. }

  1182. static CORE_ADDR
  1183. ‌frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
  1184.                                 struct target_ops *targ)
  1185. {
  1186.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1187.   CORE_ADDR entry_point;
  1188.   CORE_ADDR got_address;

  1190.   entry_point = get_target_memory_unsigned (targ, addr, 4, byte_order);
  1191.   got_address = get_target_memory_unsigned (targ, addr + 4, 4, byte_order);

  1193.   if (got_address == frv_fdpic_find_global_pointer (entry_point))
  1194.     return entry_point;
  1195.   else
  1196.     return addr;
  1197. }

  1199. static CORE_ADDR
  1200. ‌frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
  1201.                      struct regcache *regcache, CORE_ADDR bp_addr,
  1202.                      int nargs, struct value **args, CORE_ADDR sp,
  1203.                      int struct_return, CORE_ADDR struct_addr)
  1204. {
  1205.   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  1206.   int argreg;
  1207.   int argnum;
  1208.   const gdb_byte *val;
  1209.   gdb_byte valbuf[4];
  1210.   struct value *arg;
  1211.   struct type *arg_type;
  1212.   int len;
  1213.   enum type_code typecode;
  1214.   CORE_ADDR regval;
  1215.   int stack_space;
  1216.   int stack_offset;
  1217.   enum frv_abi abi = frv_abi (gdbarch);
  1218.   CORE_ADDR func_addr = find_function_addr (function, NULL);

  1220. #if 0
  1221.   printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
  1222.          nargs, (int) sp, struct_return, struct_addr);
  1223. #endif

  1225.   stack_space = 0;
  1226.   for (argnum = 0; argnum < nargs; ++argnum)
  1227.     stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);

  1229.   stack_space -= (6 * 4);
  1230.   if (stack_space > 0)
  1231.     sp -= stack_space;

  1233.   /* Make sure stack is dword aligned.  */
  1234.   sp = align_down (sp, 8);

  1236.   stack_offset = 0;

  1238.   argreg = 8;

  1240.   if (struct_return)
  1241.     regcache_cooked_write_unsigned (regcache, struct_return_regnum,
  1242.                                     struct_addr);

  1244.   for (argnum = 0; argnum < nargs; ++argnum)
  1245.     {
  1246.       arg = args[argnum];
  1247.       arg_type = check_typedef (value_type (arg));
  1248.       len = TYPE_LENGTH (arg_type);
  1249.       typecode = TYPE_CODE (arg_type);

  1251.       if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
  1252.         {
  1253.           store_unsigned_integer (valbuf, 4, byte_order,
  1254.                                   value_address (arg));
  1255.           typecode = TYPE_CODE_PTR;
  1256.           len = 4;
  1257.           val = valbuf;
  1258.         }
  1259.       else if (abi == FRV_ABI_FDPIC
  1260.                && len == 4
  1261.                && typecode == TYPE_CODE_PTR
  1262.                && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
  1263.         {
  1264.           /* The FDPIC ABI requires function descriptors to be passed instead
  1265.              of entry points.  */
  1266.           CORE_ADDR addr = extract_unsigned_integer
  1267.                              (value_contents (arg), 4, byte_order);
  1268.           addr = find_func_descr (gdbarch, addr);
  1269.           store_unsigned_integer (valbuf, 4, byte_order, addr);
  1270.           typecode = TYPE_CODE_PTR;
  1271.           len = 4;
  1272.           val = valbuf;
  1273.         }
  1274.       else
  1275.         {
  1276.           val = value_contents (arg);
  1277.         }

  1279.       while (len > 0)
  1280.         {
  1281.           int partial_len = (len < 4 ? len : 4);

  1283.           if (argreg < 14)
  1284.             {
  1285.               regval = extract_unsigned_integer (val, partial_len, byte_order);
  1286. #if 0
  1287.               printf("  Argnum %d data %x -> reg %d\n",
  1288.                      argnum, (int) regval, argreg);
  1289. #endif
  1290.               regcache_cooked_write_unsigned (regcache, argreg, regval);
  1291.               ++argreg;
  1292.             }
  1293.           else
  1294.             {
  1295. #if 0
  1296.               printf("  Argnum %d data %x -> offset %d (%x)\n",
  1297.                      argnum, *((int *)val), stack_offset,
  1298.                      (int) (sp + stack_offset));
  1299. #endif
  1300.               write_memory (sp + stack_offset, val, partial_len);
  1301.               stack_offset += align_up (partial_len, 4);
  1302.             }
  1303.           len -= partial_len;
  1304.           val += partial_len;
  1305.         }
  1306.     }

  1308.   /* Set the return address.  For the frv, the return breakpoint is
  1309.      always at BP_ADDR.  */
  1310.   regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);

  1312.   if (abi == FRV_ABI_FDPIC)
  1313.     {
  1314.       /* Set the GOT register for the FDPIC ABI.  */
  1315.       regcache_cooked_write_unsigned
  1316.         (regcache, first_gpr_regnum + 15,
  1317.          frv_fdpic_find_global_pointer (func_addr));
  1318.     }

  1320.   /* Finally, update the SP register.  */
  1321.   regcache_cooked_write_unsigned (regcache, sp_regnum, sp);

  1323.   return sp;
  1324. }

  1326. static void
  1327. ‌frv_store_return_value (struct type *type, struct regcache *regcache,
  1328.                         const gdb_byte *valbuf)
  1329. {
  1330.   int len = TYPE_LENGTH (type);

  1332.   if (len <= 4)
  1333.     {
  1334.       bfd_byte val[4];
  1335.       memset (val, 0, sizeof (val));
  1336.       memcpy (val + (4 - len), valbuf, len);
  1337.       regcache_cooked_write (regcache, 8, val);
  1338.     }
  1339.   else if (len == 8)
  1340.     {
  1341.       regcache_cooked_write (regcache, 8, valbuf);
  1342.       regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
  1343.     }
  1344.   else
  1345.     internal_error (__FILE__, __LINE__,
  1346.                     _("Don't know how to return a %d-byte value."), len);
  1347. }

  1349. static enum return_value_convention
  1350. ‌frv_return_value (struct gdbarch *gdbarch, struct value *function,
  1351.                   struct type *valtype, struct regcache *regcache,
  1352.                   gdb_byte *readbuf, const gdb_byte *writebuf)
  1353. {
  1354.   int struct_return = TYPE_CODE (valtype) == TYPE_CODE_STRUCT
  1355.                       || TYPE_CODE (valtype) == TYPE_CODE_UNION
  1356.                       || TYPE_CODE (valtype) == TYPE_CODE_ARRAY;

  1358.   if (writebuf != NULL)
  1359.     {
  1360.       gdb_assert (!struct_return);
  1361.       frv_store_return_value (valtype, regcache, writebuf);
  1362.     }

  1364.   if (readbuf != NULL)
  1365.     {
  1366.       gdb_assert (!struct_return);
  1367.       frv_extract_return_value (valtype, regcache, readbuf);
  1368.     }

  1370.   if (struct_return)
  1371.     return RETURN_VALUE_STRUCT_CONVENTION;
  1372.   else
  1373.     return RETURN_VALUE_REGISTER_CONVENTION;
  1374. }

  1376. static CORE_ADDR
  1377. ‌frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
  1378. {
  1379.   return frame_unwind_register_unsigned (next_frame, pc_regnum);
  1380. }

  1382. /* Given a GDB frame, determine the address of the calling function's
  1383.    frame.  This will be used to create a new GDB frame struct.  */

  1385. static void
  1386. ‌frv_frame_this_id (struct frame_info *this_frame,
  1387.                     void **this_prologue_cache, struct frame_id *this_id)
  1388. {
  1389.   struct frv_unwind_cache *info
  1390.     = frv_frame_unwind_cache (this_frame, this_prologue_cache);
  1391.   CORE_ADDR base;
  1392.   CORE_ADDR func;
  1393.   struct bound_minimal_symbol msym_stack;
  1394.   struct frame_id id;

  1396.   /* The FUNC is easy.  */
  1397.   func = get_frame_func (this_frame);

  1399.   /* Check if the stack is empty.  */
  1400.   msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
  1401.   if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack))
  1402.     return;

  1404.   /* Hopefully the prologue analysis either correctly determined the
  1405.      frame's base (which is the SP from the previous frame), or set
  1406.      that base to "NULL".  */
  1407.   base = info->prev_sp;
  1408.   if (base == 0)
  1409.     return;

  1411.   id = frame_id_build (base, func);
  1412.   (*this_id) = id;
  1413. }

  1415. static struct value *
  1416. ‌frv_frame_prev_register (struct frame_info *this_frame,
  1417.                          void **this_prologue_cache, int regnum)
  1418. {
  1419.   struct frv_unwind_cache *info
  1420.     = frv_frame_unwind_cache (this_frame, this_prologue_cache);
  1421.   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
  1422. }

  1424. ‌static const struct frame_unwind frv_frame_unwind = {
  1425.   NORMAL_FRAME,
  1426.   default_frame_unwind_stop_reason,
  1427.   frv_frame_this_id,
  1428.   frv_frame_prev_register,
  1429.   NULL,
  1430.   default_frame_sniffer
  1431. };

  1433. static CORE_ADDR
  1434. ‌frv_frame_base_address (struct frame_info *this_frame, void **this_cache)
  1435. {
  1436.   struct frv_unwind_cache *info
  1437.     = frv_frame_unwind_cache (this_frame, this_cache);
  1438.   return info->base;
  1439. }

  1441. ‌static const struct frame_base frv_frame_base = {
  1442.   &frv_frame_unwind,
  1443.   frv_frame_base_address,
  1444.   frv_frame_base_address,
  1445.   frv_frame_base_address
  1446. };

  1448. static CORE_ADDR
  1449. ‌frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
  1450. {
  1451.   return frame_unwind_register_unsigned (next_frame, sp_regnum);
  1452. }


  1455. /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
  1456.    frame.  The frame ID's base needs to match the TOS value saved by
  1457.    save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint.  */

  1459. static struct frame_id
  1460. ‌frv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
  1461. {
  1462.   CORE_ADDR sp = get_frame_register_unsigned (this_frame, sp_regnum);
  1463.   return frame_id_build (sp, get_frame_pc (this_frame));
  1464. }

  1466. static struct gdbarch *
  1467. ‌frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
  1468. {
  1469.   struct gdbarch *gdbarch;
  1470.   struct gdbarch_tdep *var;
  1471.   int elf_flags = 0;

  1473.   /* Check to see if we've already built an appropriate architecture
  1474.      object for this executable.  */
  1475.   arches = gdbarch_list_lookup_by_info (arches, &info);
  1476.   if (arches)
  1477.     return arches->gdbarch;

  1479.   /* Select the right tdep structure for this variant.  */
  1480.   var = new_variant ();
  1481.   switch (info.bfd_arch_info->mach)
  1482.     {
  1483.     case bfd_mach_frv:
  1484.     case bfd_mach_frvsimple:
  1485.     case bfd_mach_fr500:
  1486.     case bfd_mach_frvtomcat:
  1487.     case bfd_mach_fr550:
  1488.       set_variant_num_gprs (var, 64);
  1489.       set_variant_num_fprs (var, 64);
  1490.       break;

  1492.     case bfd_mach_fr400:
  1493.     case bfd_mach_fr450:
  1494.       set_variant_num_gprs (var, 32);
  1495.       set_variant_num_fprs (var, 32);
  1496.       break;

  1498.     default:
  1499.       /* Never heard of this variant.  */
  1500.       return 0;
  1501.     }

  1503.   /* Extract the ELF flags, if available.  */
  1504.   if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
  1505.     elf_flags = elf_elfheader (info.abfd)->e_flags;

  1507.   if (elf_flags & EF_FRV_FDPIC)
  1508.     set_variant_abi_fdpic (var);

  1510.   if (elf_flags & EF_FRV_CPU_FR450)
  1511.     set_variant_scratch_registers (var);

  1513.   gdbarch = gdbarch_alloc (&info, var);

  1515.   set_gdbarch_short_bit (gdbarch, 16);
  1516.   set_gdbarch_int_bit (gdbarch, 32);
  1517.   set_gdbarch_long_bit (gdbarch, 32);
  1518.   set_gdbarch_long_long_bit (gdbarch, 64);
  1519.   set_gdbarch_float_bit (gdbarch, 32);
  1520.   set_gdbarch_double_bit (gdbarch, 64);
  1521.   set_gdbarch_long_double_bit (gdbarch, 64);
  1522.   set_gdbarch_ptr_bit (gdbarch, 32);

  1524.   set_gdbarch_num_regs (gdbarch, frv_num_regs);
  1525.   set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);

  1527.   set_gdbarch_sp_regnum (gdbarch, sp_regnum);
  1528.   set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
  1529.   set_gdbarch_pc_regnum (gdbarch, pc_regnum);

  1531.   set_gdbarch_register_name (gdbarch, frv_register_name);
  1532.   set_gdbarch_register_type (gdbarch, frv_register_type);
  1533.   set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);

  1535.   set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
  1536.   set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);

  1538.   set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
  1539.   set_gdbarch_skip_main_prologue (gdbarch, frv_skip_main_prologue);
  1540.   set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
  1541.   set_gdbarch_adjust_breakpoint_address
  1542.     (gdbarch, frv_adjust_breakpoint_address);

  1544.   set_gdbarch_return_value (gdbarch, frv_return_value);

  1546.   /* Frame stuff.  */
  1547.   set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
  1548.   set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
  1549.   set_gdbarch_frame_align (gdbarch, frv_frame_align);
  1550.   frame_base_set_default (gdbarch, &frv_frame_base);
  1551.   /* We set the sniffer lower down after the OSABI hooks have been
  1552.      established.  */

  1554.   /* Settings for calling functions in the inferior.  */
  1555.   set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
  1556.   set_gdbarch_dummy_id (gdbarch, frv_dummy_id);

  1558.   /* Settings that should be unnecessary.  */
  1559.   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);

  1561.   /* Hardware watchpoint / breakpoint support.  */
  1562.   switch (info.bfd_arch_info->mach)
  1563.     {
  1564.     case bfd_mach_frv:
  1565.     case bfd_mach_frvsimple:
  1566.     case bfd_mach_fr500:
  1567.     case bfd_mach_frvtomcat:
  1568.       /* fr500-style hardware debugging support.  */
  1569.       var->num_hw_watchpoints = 4;
  1570.       var->num_hw_breakpoints = 4;
  1571.       break;

  1573.     case bfd_mach_fr400:
  1574.     case bfd_mach_fr450:
  1575.       /* fr400-style hardware debugging support.  */
  1576.       var->num_hw_watchpoints = 2;
  1577.       var->num_hw_breakpoints = 4;
  1578.       break;

  1580.     default:
  1581.       /* Otherwise, assume we don't have hardware debugging support.  */
  1582.       var->num_hw_watchpoints = 0;
  1583.       var->num_hw_breakpoints = 0;
  1584.       break;
  1585.     }

  1587.   set_gdbarch_print_insn (gdbarch, print_insn_frv);
  1588.   if (frv_abi (gdbarch) == FRV_ABI_FDPIC)
  1589.     set_gdbarch_convert_from_func_ptr_addr (gdbarch,
  1590.                                             frv_convert_from_func_ptr_addr);

  1592.   set_solib_ops (gdbarch, &frv_so_ops);

  1594.   /* Hook in ABI-specific overrides, if they have been registered.  */
  1595.   gdbarch_init_osabi (info, gdbarch);

  1597.   /* Set the fallback (prologue based) frame sniffer.  */
  1598.   frame_unwind_append_unwinder (gdbarch, &frv_frame_unwind);

  1600.   /* Enable TLS support.  */
  1601.   set_gdbarch_fetch_tls_load_module_address (gdbarch,
  1602.                                              frv_fetch_objfile_link_map);

  1604.   return gdbarch;
  1605. }

  1607. void
  1608. ‌_initialize_frv_tdep (void)
  1609. {
  1610.   register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);
  1611. }